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vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_3d/config 2 files changed +31
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+ ##############################################
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+ # Configuration file for running experiments
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+ ##############################################
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+
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+ # Path to directory of circuits to use
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+ circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
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+
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+ # Path to directory of architectures to use
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+ archs_dir=arch/multi_die/simple_arch
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+
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+ # Add circuits to list to sweep
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+ circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif
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+
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+ # Add architectures to list to sweep
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+ arch_list_add=k6_frac_N10_40nm.xml
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+
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+ # Parse info and how to parse
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+ parse_file=vpr_fixed_chan_width.txt
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+ parse_file=vpr_parse_second_file.txt
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+
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+ # How to parse QoR info
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+ qor_parse_file=qor_rr_graph.txt
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+
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+ # Pass requirements
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+ pass_requirements_file=pass_requirements_verify_rr_graph.txt
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+
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+ # Script parameters
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+ script_params = -verify_rr_graph --route_chan_width 100
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+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time
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+ k4_N4_90nm.xml stereovision3.v common 1.67 vpr 56.43 MiB -1 -1 0.45 25384 6 0.13 -1 -1 35724 -1 -1 26 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 57788 10 2 186 188 1 49 38 8 8 64 clb auto 18.2 MiB 0.02 224 56.4 MiB 0.01 0.00 2.40278 -103.067 -2.40278 2.40278 0.00 0.000119899 9.7708e-05 0.00253947 0.0021251 203 186 417 22870 4288 80255.5 57962.3 276194. 4315.53 12 2.46522 2.46522 -111.211 -2.46522 -0.0734 -0.0734 56.4 MiB 0.01 0.00769657 0.00673067 56.4 MiB 0.03
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+ k6_frac_N10_40nm.xml stereovision3.v common 1.49 vpr 57.75 MiB -1 -1 0.45 25728 5 0.13 -1 -1 35988 -1 -1 7 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 59136 10 2 181 183 1 37 19 5 5 25 clb auto 19.5 MiB 0.05 109 57.8 MiB 0.01 0.00 1.93928 -79.4364 -1.93928 1.93928 0.00 0.000117405 9.5811e-05 0.00377247 0.00328288 95 62 85 1742 528 485046 377258 99699.4 3987.98 5 2.07705 2.07705 -87.1807 -2.07705 0 0 57.8 MiB 0.01 0.00934793 0.00856098 57.8 MiB 0.01
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