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4 | 4 | - 40 nm technology
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5 | 5 | - General purpose logic block:
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6 | 6 | K = 6, N = 10
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7 |
| - - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 |
| 7 | + - Routing architecture: L = 4, fc_in = 0.15, fc_out = 0.15 |
| 8 | + - Unidirectional (mux-based) routing |
| 9 | +
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8 | 10 |
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9 | 11 | Details on Modelling:
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10 | 12 |
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11 | 13 | Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs nor any heterogeneous blocks.
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12 |
| -
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| 14 | + The delays and areas are based on a mix of values from commercial 40 nm |
| 15 | + FPGAs with a comparable architecture and 40 nm interconnect and |
| 16 | + transistor models. |
13 | 17 |
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14 | 18 | Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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15 | 19 | -->
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16 | 20 | <architecture>
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17 | 21 | <!--
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18 | 22 | ODIN II specific config begins
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19 |
| - Describes the types of user-specified netlist blocks (in blif, this corresponds to |
20 |
| - ".model [type_of_block]") that this architecture supports. |
21 |
| -
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22 |
| - Note: Basic LUTs, I/Os, and flip-flops are not included here as there are |
23 |
| - already special structures in blif (.names, .input, .output, and .latch) |
24 |
| - that describe them. |
| 23 | + This part of the architecture file describes the "primitives" |
| 24 | + that exist in a device to the synthesis tool used to "elaborate" |
| 25 | + verilog into these primitives (which is called ODIN-II). |
| 26 | + Basic LUTs, I/Os and FFs are built into the language used by this |
| 27 | + flow (blif keywords .names, .input, .output and .latch), so they |
| 28 | + don't have to be described here. |
| 29 | + |
| 30 | + For this lab you are also given the benchmark netlists after |
| 31 | + synthesis is complete (in the blif directory), so you don't need |
| 32 | + to run ODIN II. |
25 | 33 | -->
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26 | 34 | <models>
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27 | 35 | </models>
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| 36 | + <!-- ODIN II specific config ends --> |
| 37 | + |
| 38 | + <!-- Descritions of the physical tiles that exist on the die begins --> |
28 | 39 | <tiles>
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29 | 40 | <tile name="io" area="0">
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30 | 41 | <sub_tile name="io" capacity="8">
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34 | 45 | <input name="outpad" num_pins="1"/>
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35 | 46 | <output name="inpad" num_pins="1"/>
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36 | 47 | <clock name="clock" num_pins="1"/>
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37 |
| - <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> |
| 48 | + <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/> |
| 49 | + <!-- IOs go on the periphery of the FPGA in this |
| 50 | + architecture. Since I don't want to define four |
| 51 | + different physical I/Os for the left, right, top, |
| 52 | + and bottom sides just say each pin of the I/O |
| 53 | + block is accessible from all four sides so we can |
| 54 | + reach routing channels on some side of the block |
| 55 | + no matter which side of the chip we're on. |
| 56 | + --> |
38 | 57 | <pinlocations pattern="custom">
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39 | 58 | <loc side="left">io.outpad io.inpad io.clock</loc>
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40 | 59 | <loc side="top">io.outpad io.inpad io.clock</loc>
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43 | 62 | </pinlocations>
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44 | 63 | </sub_tile>
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45 | 64 | </tile>
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46 |
| - <tile name="clb" area="53894"> |
| 65 | + |
| 66 | + <!-- Define general purpose logic block (CLB) begin --> |
| 67 | + <!-- Area below is for everything inside the |
| 68 | + logic block (LUTs, FFs, intra-cluster |
| 69 | + routing). It's a bit on the low side given the large crossbars in this |
| 70 | + architecture - more appropriate for a lower-cost |
| 71 | + FPGA with smaller transistors and narrower metal. |
| 72 | + --> |
| 73 | + <tile name="clb" area="18000"> |
| 74 | + <!-- We can place a clustered block of type clb on a tile location |
| 75 | + of type clb. |
| 76 | + --> |
47 | 77 | <sub_tile name="clb">
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48 | 78 | <equivalent_sites>
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49 | 79 | <site pb_type="clb" pin_mapping="direct"/>
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50 | 80 | </equivalent_sites>
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| 81 | + |
| 82 | + <!-- We have a full crossbar between the cluster inputs and the |
| 83 | + LUT inputs, so the router can route to *any* input or from |
| 84 | + *any* output on the logic block. Hence mark the logic block |
| 85 | + inputs as fully logically equivalent (swappable by the router) and also the |
| 86 | + logic block outputs as logically equivalent, which means |
| 87 | + they can also be swapped by the router. |
| 88 | + --> |
| 89 | + |
51 | 90 | <input name="I" num_pins="40" equivalent="full"/>
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52 | 91 | <output name="O" num_pins="10" equivalent="instance"/>
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53 | 92 | <clock name="clk" num_pins="1"/>
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54 |
| - <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> |
| 93 | + <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/> |
55 | 94 | <pinlocations pattern="spread"/>
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56 | 95 | </sub_tile>
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57 | 96 | </tile>
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58 | 97 | </tiles>
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59 |
| - <!-- ODIN II specific config ends --> |
60 |
| - <!-- Physical descriptions begin --> |
| 98 | + <!-- Physical tile descriptions end --> |
| 99 | + |
| 100 | + <!-- Chip layout (in terms of where tiles are) begins --> |
61 | 101 | <layout>
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62 | 102 | <auto_layout aspect_ratio="1.0">
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63 | 103 | <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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67 | 107 | <fill type="clb" priority="10"/>
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68 | 108 | </auto_layout>
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69 | 109 | </layout>
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| 110 | + <!-- Chip layout ends --> |
| 111 | + |
| 112 | + <!-- Electrical and inter-cluster (general) routing description begins --> |
70 | 113 | <device>
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71 |
| - <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM |
72 |
| - models. We are modifying the delay values however, to include metal C and R, which allows more architecture |
73 |
| - experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS |
74 |
| - (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of |
75 |
| - 45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping |
76 |
| - RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately |
77 |
| - lined up with Stratix IV. |
78 |
| - We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm). |
79 |
| - Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm). |
80 |
| - The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file |
81 |
| - by 2.5x when looking up in Jeff's tables. |
82 |
| - The delay values are lined up with Stratix IV, which has an architecture similar to this |
83 |
| - proposed FPGA, and which is also 40 nm |
84 |
| - C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage |
85 |
| - 4x minimum drive strength buffer. --> |
| 114 | + <!-- Some area and timing parameters --> |
86 | 115 | <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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87 | 116 | <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
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88 | 117 | area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
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92 | 121 | <x distr="uniform" peak="1.000000"/>
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93 | 122 | <y distr="uniform" peak="1.000000"/>
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94 | 123 | </chan_width_distr>
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| 124 | + |
| 125 | + <!-- Define the switch block pattern (pattern of switches between inter-tile routing wires) |
| 126 | + The Wilton switch block is a sample pattern; you can use custom switch blocks for more control --> |
95 | 127 | <switch_block type="wilton" fs="3"/>
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| 128 | + |
| 129 | + <!-- Set which switch to use for input connection blocks. Only affects timing and area, not connectivity --> |
96 | 130 | <connection_block input_switch_name="ipin_cblock"/>
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97 | 131 | </device>
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98 | 132 | <switchlist>
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99 | 133 | <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
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100 | 134 | book area formula. This means the mux transistors are about 5x minimum drive strength.
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101 | 135 | We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
102 |
| - mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume |
103 |
| - the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed |
104 |
| - by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified |
105 |
| - buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive. |
106 |
| - I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout |
107 |
| - (diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples. |
108 |
| - The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by |
109 |
| - 2.5x when looking up in Jeff's tables. |
110 |
| - Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. |
111 |
| - This also leads to the switch being 46% of the total wire delay, which is reasonable. --> |
| 136 | + mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. |
| 137 | + --> |
112 | 138 | <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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113 | 139 | <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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114 | 140 | <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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115 | 141 | </switchlist>
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116 | 142 | <segmentlist>
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117 | 143 | <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
118 |
| - With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems |
119 |
| - reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> |
| 144 | + Wires of this pitch will fit over a 90 nm |
| 145 | + high logic tile (which is about the height of a Stratix IV logic tile). |
| 146 | + I'm using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. |
| 147 | + length below is in units of logic blocks, and Rmetal and Cmetal are |
| 148 | + per logic block passed, so wire delay adapts automatically if you change the |
| 149 | + length=? value. --> |
| 150 | + |
| 151 | + <!-- Currently only one type of routing wire, which |
| 152 | + is of length 4 and has switches to every connection |
| 153 | + box (4 of them) and switch box (5 of them) |
| 154 | + it passes. You can change wirelengths just by changing the length="?" values |
| 155 | + and changing the number of 1's (or 0's) in the <sb type and <cb type lines to |
| 156 | + match the number of switch blocks and connection blocks a wire of that length |
| 157 | + would span. --> |
120 | 158 | <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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121 | 159 | <mux name="0"/>
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122 | 160 | <sb type="pattern">1 1 1 1 1</sb>
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123 | 161 | <cb type="pattern">1 1 1 1</cb>
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124 | 162 | </segment>
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125 | 163 | </segmentlist>
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| 164 | + <!-- Electrical and inter-cluster routing description ends --> |
| 165 | + |
| 166 | + <!-- Description of the capabilities (number of BLEs, modes) and local interconnect in |
| 167 | + each type of complex (clustered) block (e.g. LBs) begins |
| 168 | + --> |
126 | 169 | <complexblocklist>
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127 | 170 | <!-- Define I/O pads begin -->
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128 |
| - <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> |
129 | 171 | <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
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130 | 172 | <pb_type name="io">
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131 | 173 | <input name="outpad" num_pins="1"/>
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132 | 174 | <output name="inpad" num_pins="1"/>
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133 | 175 | <clock name="clock" num_pins="1"/>
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134 | 176 | <!-- IOs can operate as either inputs or outputs.
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135 |
| - Delays below come from Ian Kuon. They are small, so they should be interpreted as |
136 |
| - the delays to and from registers in the I/O (and generally I/Os are registered |
137 |
| - today and that is when you timing analyze them. |
| 177 | + The delays below are to and from registers in the I/O (and generally I/Os are registered |
| 178 | + today). |
138 | 179 | -->
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139 | 180 | <mode name="inpad">
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140 | 181 | <pb_type name="inpad" blif_model=".input" num_pb="1">
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156 | 197 | </direct>
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157 | 198 | </interconnect>
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158 | 199 | </mode>
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159 |
| - <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> |
160 |
| - <!-- IOs go on the periphery of the FPGA, for consistency, |
161 |
| - make it physically equivalent on all sides so that only one definition of I/Os is needed. |
162 |
| - If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA |
163 |
| - --> |
164 |
| - <!-- Place I/Os on the sides of the FPGA --> |
| 200 | + |
| 201 | + <!-- Not modeling I/O power for now --> |
165 | 202 | <power method="ignore"/>
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166 | 203 | </pb_type>
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167 | 204 | <!-- Define I/O pads ends -->
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| 205 | + |
168 | 206 | <!-- Define general purpose logic block (CLB) begin -->
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169 |
| - <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor |
170 |
| - area is 60 L^2 yields a tile area of 84375 MWTAs. |
171 |
| - Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area |
172 |
| - This means that only 37% of our area is in the general routing, and 63% is inside the logic |
173 |
| - block. Note that the crossbar / local interconnect is considered part of the logic block |
174 |
| - area in this analysis. That is a lower proportion of of routing area than most academics |
175 |
| - assume, but note that the total routing area really includes the crossbar, which would push |
176 |
| - routing area up significantly, we estimate into the ~70% range. |
177 |
| - --> |
| 207 | + <!-- Area below is for everything inside the |
| 208 | + logic block (LUTs, FFs, intra-cluster |
| 209 | + routing). |
| 210 | + --> |
178 | 211 | <pb_type name="clb">
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179 | 212 | <input name="I" num_pins="40" equivalent="full"/>
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180 | 213 | <output name="O" num_pins="10" equivalent="instance"/>
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198 | 231 | <input name="in" num_pins="6" port_class="lut_in"/>
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199 | 232 | <output name="out" num_pins="1" port_class="lut_out"/>
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200 | 233 | <!-- LUT timing using delay matrix -->
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201 |
| - <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, |
202 |
| - we instead take the average of these numbers to get more stable results |
| 234 | + <!-- These are the delay per LUT input on a Stratix IV LUT. |
| 235 | + The average is 261 ps, and inputs earlier in the mux tree are slower. |
| 236 | + --> |
| 237 | + <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> |
203 | 238 | 82e-12
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204 | 239 | 173e-12
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205 | 240 | 261e-12
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206 | 241 | 263e-12
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207 | 242 | 398e-12
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208 | 243 | 397e-12
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209 |
| - --> |
210 |
| - <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> |
211 |
| - 261e-12 |
212 |
| - 261e-12 |
213 |
| - 261e-12 |
214 |
| - 261e-12 |
215 |
| - 261e-12 |
216 |
| - 261e-12 |
217 | 244 | </delay_matrix>
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218 | 245 | </pb_type>
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219 | 246 | <!-- Define flip-flop -->
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224 | 251 | <T_setup value="66e-12" port="ff.D" clock="clk"/>
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225 | 252 | <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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226 | 253 | </pb_type>
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| 254 | + |
| 255 | + <!-- many lines below to describe the interconnect |
| 256 | + wires, muxes and crossbars inside a cluster. |
| 257 | + --> |
227 | 258 | <interconnect>
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228 | 259 | <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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229 | 260 | <direct name="direct2" input="lut6.out" output="ff.D">
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262 | 293 | </complete>
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263 | 294 | <complete name="clks" input="clb.clk" output="fle[9:0].clk">
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264 | 295 | </complete>
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265 |
| - <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. |
266 |
| - By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, |
267 |
| - then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more |
268 |
| - naive specification). |
| 296 | + |
| 297 | + <!-- The BLE outputs are directly connected to the |
| 298 | + CLB (cluster) outputs. |
269 | 299 | -->
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270 | 300 | <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
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271 | 301 | </interconnect>
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272 |
| - <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> |
273 |
| - <!-- Place this general purpose logic block in any unspecified column --> |
274 | 302 | </pb_type>
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275 | 303 | <!-- Define general purpose logic block (CLB) ends -->
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276 | 304 | </complexblocklist>
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