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sdamghansdamghan
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Merge pull request #1844 from sdamghan/yosys+vtr
Yosys+VTR
2 parents 467ad22 + 541b74a commit 851c8bf

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‎.github/kokoro/continuous/yosys_test.cfg

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# Format: //devtools/kokoro/config/proto/build.proto
2-
# vtr_reg_yosys_odin test runs the VTR benchmarks through
3-
# the entire VTR with Yosys+Odin-II as the first CAD tool
2+
# vtr_reg_yosys test runs the VTR benchmarks through
3+
# the entire VTR with Yosys as the first CAD tool
44

55
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
66

@@ -48,12 +48,12 @@ env_vars {
4848
#Use default build configuration
4949
env_vars {
5050
key: "VTR_CMAKE_PARAMS"
51-
value: ""
51+
value: "-DWITH_YOSYS=ON"
5252
}
5353

5454
env_vars {
5555
key: "VTR_TEST"
56-
value: "odin_reg_strong"
56+
value: "vtr_reg_yosys"
5757
}
5858

5959
#Options for run_reg_test.py
@@ -65,5 +65,5 @@ env_vars {
6565

6666
env_vars {
6767
key: "NUM_CORES"
68-
value: "3"
69-
}
68+
value: "8"
69+
}

‎.github/kokoro/presubmit/yosys_test.cfg

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# Format: //devtools/kokoro/config/proto/build.proto
2-
# vtr_reg_yosys_odin test runs the VTR benchmarks through
3-
# the entire VTR with Yosys+Odin-II as the first CAD tool
2+
# vtr_reg_yosys test runs the VTR benchmarks through
3+
# the entire VTR with Yosys as the first CAD tool
44

55
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
66

@@ -48,12 +48,12 @@ env_vars {
4848
#Use default build configuration
4949
env_vars {
5050
key: "VTR_CMAKE_PARAMS"
51-
value: ""
51+
value: "-DWITH_YOSYS=ON"
5252
}
5353

5454
env_vars {
5555
key: "VTR_TEST"
56-
value: "odin_reg_strong"
56+
value: "vtr_reg_yosys"
5757
}
5858

5959
#Options for run_reg_test.py

‎CMakeLists.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ option(ODIN_TIDY "Enable building odin with clang tidy" OFF)
5252
option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
5353

5454
# Allow the user to enable building Yosys
55+
option(WITH_YOSYS "Enable building Yosys" OFF)
5556
option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
5657

5758
set(VTR_VERSION_MAJOR 8)
@@ -381,7 +382,10 @@ if(${WITH_ABC})
381382
add_subdirectory(ace2)
382383
endif()
383384
add_subdirectory(utils)
384-
if(${WITH_ODIN})
385+
# define cmake params to compile Yosys
386+
if(${WITH_YOSYS})
387+
add_definitions("-D_YOSYS_")
388+
elseif(${WITH_ODIN})
385389
add_subdirectory(ODIN_II)
386390
# blifexplorer depends on odin
387391
if(${WITH_BLIFEXPLORER})

‎ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,15 +58,15 @@
5858
"Latch Drivers": 1,
5959
"Pi": 273,
6060
"Po": 193,
61-
"logic element": 4141,
62-
"latch": 857,
63-
"Adder": 136,
61+
"logic element": 4204,
62+
"latch": 871,
63+
"Adder": 151,
6464
"Memory": 32,
6565
"generic logic size": 4,
6666
"Longest Path": 428,
6767
"Average Path": 4,
68-
"Estimated LUTs": 4435,
69-
"Total Node": 5167
68+
"Estimated LUTs": 4510,
69+
"Total Node": 5259
7070
},
7171
"large/des_area/k6_frac_N10_frac_chain_mem32K_40nm": {
7272
"test_name": "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm",

‎ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -101,15 +101,15 @@
101101
"Latch Drivers": 1,
102102
"Pi": 273,
103103
"Po": 193,
104-
"logic element": 4141,
105-
"latch": 857,
106-
"Adder": 136,
104+
"logic element": 4204,
105+
"latch": 871,
106+
"Adder": 151,
107107
"Memory": 32,
108108
"generic logic size": 4,
109109
"Longest Path": 428,
110110
"Average Path": 4,
111-
"Estimated LUTs": 4435,
112-
"Total Node": 5167
111+
"Estimated LUTs": 4510,
112+
"Total Node": 5259
113113
},
114114
"vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm": {
115115
"test_name": "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm",

‎ODIN_II/regression_test/benchmark/verilog/full/mcml.v

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
17761776

17771777
assign const_zero = 1'b0;
17781778
assign const_zero_data = 32'b00000000000000000000000000000000;
1779-
assign dont_care_out = 32'b00000000000000000000000000000000;
1779+
// assign dont_care_out = 32'b00000000000000000000000000000000;
17801780

17811781
defparam dpram1.ADDR_WIDTH = 13;
17821782
defparam dpram1.DATA_WIDTH = 32;
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
18131813

18141814
assign const_zero = 1'b0;
18151815
assign const_zero_data = 32'b00000000000000000000000000000000;
1816-
assign dont_care_out = 32'b00000000000000000000000000000000;
1816+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18171817

18181818
defparam dpram1.ADDR_WIDTH = 13;
18191819
defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
18501850

18511851
assign const_zero = 1'b0;
18521852
assign const_zero_data = 32'b00000000000000000000000000000000;
1853-
assign dont_care_out = 32'b00000000000000000000000000000000;
1853+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18541854

18551855
defparam dpram1.ADDR_WIDTH = 13;
18561856
defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
18871887

18881888
assign const_zero = 1'b0;
18891889
assign const_zero_data = 32'b00000000000000000000000000000000;
1890-
assign dont_care_out = 32'b00000000000000000000000000000000;
1890+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18911891

18921892
defparam dpram1.ADDR_WIDTH = 13;
18931893
defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
19231923

19241924
assign const_zero = 1'b0;
19251925
assign const_zero_data = 36'b000000000000000000000000000000000000;
1926-
assign dont_care_out = 36'b000000000000000000000000000000000000;
1926+
// assign dont_care_out = 36'b000000000000000000000000000000000000;
19271927

19281928
defparam dpram1.ADDR_WIDTH = 16;
19291929
defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
19591959

19601960
assign const_zero = 1'b0;
19611961
assign const_zero_data = 18'b000000000000000000;
1962-
assign dont_care_out = 18'b000000000000000000;
1962+
// assign dont_care_out = 18'b000000000000000000;
19631963

19641964
defparam dpram1.ADDR_WIDTH = 16;
19651965
defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
19951995

19961996
assign const_zero = 1'b0;
19971997
assign const_zero_data = 8'b00000000;
1998-
assign dont_care_out = 8'b00000000;
1998+
// assign dont_care_out = 8'b00000000;
19991999

20002000
defparam dpram1.ADDR_WIDTH = 16;
20012001
defparam dpram1.DATA_WIDTH = 8;

‎ODIN_II/regression_test/benchmark/verilog/large/boundtop.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ wire[63:0] tldata;
222222
resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0);
223223
rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0);
224224
boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
225-
boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
225+
boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
226226
resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0);
227227

228228
assign raygroupout = raygroupout01 | raygroupout10 ;
@@ -287,7 +287,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ;
287287

288288
resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0);
289289

290-
// global reset as an output is undriven!
290+
// global reset as an output should be driven!
291291
assign globalreset = pglobalreset;
292292

293293
endmodule
@@ -2821,4 +2821,4 @@ endmodule
28212821
end
28222822
end
28232823
end
2824-
endmodule
2824+
endmodule

‎libs/EXTERNAL/CMakeLists.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@ if(VPR_USE_EZGL STREQUAL "on")
1414
add_subdirectory(libezgl)
1515
endif()
1616

17-
# The VTR root CMakeFile initializes the ODIN_USE_YOSYS
17+
# The VTR root CMakeFile initializes the ODIN_USE_YOSYS or WITH_YOSYS
1818
# Yosys is compiled only if the user ask for it
19-
if(${ODIN_USE_YOSYS})
19+
if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
2020
add_subdirectory(libyosys)
2121
endif()
2222

‎libs/EXTERNAL/libyosys/CMakeLists.txt

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,41 @@
11
cmake_minimum_required(VERSION 3.9)
22

3-
# [KNOWN_ISSUE]: if ODIN_USE_YOSYS is active, abc will be compiled
4-
# for the second time inside Yosys, since Yosys uses a different
5-
# version of abc
63
project("libyosys")
74

85
# Create a target out of the library compilation result
96
SET(LIB_FILE ${CMAKE_CURRENT_SOURCE_DIR}/libyosys.so)
107
SET(BINARY_LIB_FILE ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/libyosys.so)
8+
SET(YOSYS_EXEC ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
9+
SET(BINARY_EXEC_FILE ${CMAKE_CURRENT_BINARY_DIR}/bin/yosys)
1110
SET(YOSYS_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR})
1211

1312
# handle make program with both ninja and unix style
1413
set(MAKE_PROGRAM "$(MAKE)")
1514
# handle cppflags to suppress yosys warning with both ninja and unix style
1615
set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
1716
if(${CMAKE_GENERATOR} STREQUAL "Ninja")
18-
set(MAKE_PROGRAM "make")
19-
set(CURRENT_CPPFLAGS "-w")
17+
set(MAKE_PROGRAM "make")
18+
set(CURRENT_CPPFLAGS "-w")
2019
endif()
2120

2221
# how to build the result of the library
23-
add_custom_command(OUTPUT ${LIB_FILE} ${BINARY_LIB_FILE}
24-
COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1"
25-
CPPFLAGS=${CURRENT_CPPFLAGS}
26-
-j${CMAKE_BUILD_PARALLEL_LEVEL}
27-
PREFIX=${CMAKE_CURRENT_BINARY_DIR}
28-
> /dev/null
29-
COMMAND ${MAKE_PROGRAM} install
30-
PREFIX=${CMAKE_CURRENT_BINARY_DIR}
31-
> /dev/null
32-
COMMAND ${CMAKE_COMMAND} -E
33-
make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
34-
COMMAND ${CMAKE_COMMAND} -E
35-
copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
36-
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
22+
add_custom_command(OUTPUT ${LIB_FILE} ${BINARY_LIB_FILE} ${YOSYS_EXEC} ${BINARY_EXEC_FILE}
23+
COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" "ENABLE_ABC=0"
24+
CPPFLAGS=${CURRENT_CPPFLAGS}
25+
-j${CMAKE_BUILD_PARALLEL_LEVEL}
26+
PREFIX=${CMAKE_CURRENT_BINARY_DIR}
27+
> /dev/null
28+
COMMAND ${MAKE_PROGRAM} install
29+
PREFIX=${CMAKE_CURRENT_BINARY_DIR}
30+
> /dev/null
31+
COMMAND ${CMAKE_COMMAND} -E
32+
make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
33+
COMMAND ${CMAKE_COMMAND} -E
34+
copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
35+
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
3736

3837
# create a target out of the library compilation result
39-
add_custom_target(yosys DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
38+
add_custom_target(yosys ALL DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
4039

4140
# create an library target out of the library compilation result
4241
add_library(libyosys SHARED IMPORTED GLOBAL)
@@ -47,3 +46,6 @@ set_target_properties(libyosys
4746
PROPERTIES PREFIX "" #Avoid extra 'lib' prefix
4847
IMPORTED_LOCATION ${LIB_FILE}
4948
INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS})
49+
50+
51+
install(FILES ${YOSYS_EXEC} DESTINATION ${CMAKE_CURRENT_BINARY_DIR})

‎vtr_flow/benchmarks/verilog/arm_core.v

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4048,7 +4048,7 @@ reg [31:0] r11 = 32'hdeadbeef;
40484048
reg [31:0] r12 = 32'hdeadbeef;
40494049
reg [31:0] r13 = 32'hdeadbeef;
40504050
reg [31:0] r14 = 32'hdeadbeef;
4051-
reg [23:0] r15 = 24'hc0ffee;
4051+
reg [23:0] r15; // see line: 4272
40524052

40534053
wire [31:0] r0_out;
40544054
wire [31:0] r1_out;
@@ -4268,7 +4268,8 @@ assign r15_out_rm_nxt = { i_status_bits_flags,
42684268
i_status_bits_firq_mask,
42694269
i_pc,
42704270
i_mode_exec};
4271-
4271+
4272+
// if r15 is initialized => Yosys+ABC:A CI/CO pair share the name (u_execute.u_register_bank.r15[1]) but do not link directly
42724273
assign r15_out_rn = {6'd0, r15, 2'd0};
42734274

42744275

‎vtr_flow/benchmarks/verilog/boundtop.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ wire[63:0] tldata;
222222
resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0);
223223
rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0);
224224
boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
225-
boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
225+
boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
226226
resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0);
227227

228228
assign raygroupout = raygroupout01 | raygroupout10 ;

‎vtr_flow/benchmarks/verilog/mcml.v

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
17761776

17771777
assign const_zero = 1'b0;
17781778
assign const_zero_data = 32'b00000000000000000000000000000000;
1779-
assign dont_care_out = 32'b00000000000000000000000000000000;
1779+
// assign dont_care_out = 32'b00000000000000000000000000000000;
17801780

17811781
defparam dpram1.ADDR_WIDTH = 13;
17821782
defparam dpram1.DATA_WIDTH = 32;
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
18131813

18141814
assign const_zero = 1'b0;
18151815
assign const_zero_data = 32'b00000000000000000000000000000000;
1816-
assign dont_care_out = 32'b00000000000000000000000000000000;
1816+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18171817

18181818
defparam dpram1.ADDR_WIDTH = 13;
18191819
defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
18501850

18511851
assign const_zero = 1'b0;
18521852
assign const_zero_data = 32'b00000000000000000000000000000000;
1853-
assign dont_care_out = 32'b00000000000000000000000000000000;
1853+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18541854

18551855
defparam dpram1.ADDR_WIDTH = 13;
18561856
defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
18871887

18881888
assign const_zero = 1'b0;
18891889
assign const_zero_data = 32'b00000000000000000000000000000000;
1890-
assign dont_care_out = 32'b00000000000000000000000000000000;
1890+
// assign dont_care_out = 32'b00000000000000000000000000000000;
18911891

18921892
defparam dpram1.ADDR_WIDTH = 13;
18931893
defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
19231923

19241924
assign const_zero = 1'b0;
19251925
assign const_zero_data = 36'b000000000000000000000000000000000000;
1926-
assign dont_care_out = 36'b000000000000000000000000000000000000;
1926+
// assign dont_care_out = 36'b000000000000000000000000000000000000;
19271927

19281928
defparam dpram1.ADDR_WIDTH = 16;
19291929
defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
19591959

19601960
assign const_zero = 1'b0;
19611961
assign const_zero_data = 18'b000000000000000000;
1962-
assign dont_care_out = 18'b000000000000000000;
1962+
// assign dont_care_out = 18'b000000000000000000;
19631963

19641964
defparam dpram1.ADDR_WIDTH = 16;
19651965
defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
19951995

19961996
assign const_zero = 1'b0;
19971997
assign const_zero_data = 8'b00000000;
1998-
assign dont_care_out = 8'b00000000;
1998+
// assign dont_care_out = 8'b00000000;
19991999

20002000
defparam dpram1.ADDR_WIDTH = 16;
20012001
defparam dpram1.DATA_WIDTH = 8;

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