include more arch in benchmark

Author: jeanlego

ODIN_II/SRC/include/soft_logic_def_parser.h

@@ -47,7 +47,7 @@ typedef struct soft_sub_structure_t
 	int bitsize;
 }soft_sub_structure;
 
-void read_soft_def_file(std::string input_file_name);
+void read_soft_def_file(t_model *hard_adder_models);
 soft_sub_structure *fetch_blk(std::string, int width);
 
 

ODIN_II/SRC/include/types.h

@@ -183,6 +183,8 @@ struct global_args_t_t
 	argparse::ArgValue<bool> sim_generate_three_valued_logic;
 	// Output both falling and rising edges in the output_vectors file. (DEFAULT)
 	argparse::ArgValue<bool> sim_output_both_edges;
+	// Request to read mif file input
+	argparse::ArgValue<bool> read_mif_input;
 	// Additional pins, nets, and nodes to output.
 	argparse::ArgValue<std::vector<std::string>> sim_additional_pins;
 	// Comma-separated list of primary input pins to hold high for all cycles but the first.

ODIN_II/SRC/odin_ii.cpp

@@ -78,7 +78,16 @@ t_type_descriptor* type_descriptors;
 int block_tag;
 int num_types=0;
 
-static int synthesize_verilog()
+typedef enum
+{
+	SUCCESS,
+	ERROR_PARSE_ARCH,
+	ERROR_SYNTHESIS,
+	ERROR_PARSE_BLIF,
+
+}ODIN_ERROR_CODE;
+
+static ODIN_ERROR_CODE synthesize_verilog()
 {
 	double elaboration_time = wall_time();
 
@@ -91,14 +100,7 @@ static int synthesize_verilog()
 	register_hard_blocks();
 
 	/* get odin soft_logic definition file */
-	std::string soft_distribution(global_args.adder_def);
-	if(!hard_adders && soft_distribution == "default")
-	{
-		if(soft_distribution == "optimized")
-			soft_distribution = vtr::dirname(global_args.program_name) + "odin.soft_config";
-
-		read_soft_def_file(soft_distribution);
-	}
+	read_soft_def_file(hard_adders);
 
 	global_param_table_sc = sc_new_string_cache();
 
@@ -195,7 +197,7 @@ static int synthesize_verilog()
 	//cleanup netlist
 	free_netlist(verilog_netlist);
 
-	return 0;
+	return SUCCESS;
 }
 
 struct netlist_t_t *start_odin_ii(int argc,char **argv)
@@ -213,8 +215,6 @@ struct netlist_t_t *start_odin_ii(int argc,char **argv)
 		mkdir(DEFAULT_OUTPUT, 0755);
 	#endif
 
-	int error_code = 0;
-
 	printf("--------------------------------------------------------------------\n");
 	printf("Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)\n");
 	printf("Email: [email protected] and [email protected] for support issues\n\n");
@@ -242,30 +242,25 @@ struct netlist_t_t *start_odin_ii(int argc,char **argv)
 		} 
 		catch(vtr::VtrError& vtr_error) 
 		{
-			printf("Failed to load architecture file: %s\n", vtr_error.what());
-			error_code = 1;
+			printf("Odin Failed to load architecture file: %s with exit code%d\n", vtr_error.what(), ERROR_PARSE_ARCH);
+			exit(ERROR_PARSE_ARCH);
 		}
 	}
 
-	if(error_code)
-	{
-		printf("Odin Failed to start with exit status: %d\n", error_code);
-		terminate_odin_ii(verilog_netlist);
-		return NULL;
-	}
-
 	/* do High level Synthesis */
 	if (!global_args.blif_file)
 	{
-		error_code = synthesize_verilog();
-	}
-
-	if(error_code)
-	{
-		printf("Odin Failed to parse Verilog with exit status: %d\n", error_code);
-		return NULL;
+		ODIN_ERROR_CODE error_code = synthesize_verilog();
+		if(error_code)
+		{
+			printf("Odin Failed to parse Verilog with exit status: %d\n", error_code);
+			exit(error_code);
+		}
 	}
 
+	/*************************************************************
+	 * begin simulation section
+	 */
 	netlist_t *odin_netlist = NULL;
 
 	if(global_args.blif_file
@@ -279,6 +274,7 @@ struct netlist_t_t *start_odin_ii(int argc,char **argv)
 		{
 			char *output_file = global_args.output_file;
 			configuration.list_of_file_names = { std::string(output_file) };
+			current_parse_file =0;
 		}
 
 		try 
@@ -287,17 +283,11 @@ struct netlist_t_t *start_odin_ii(int argc,char **argv)
 		} 
 		catch(vtr::VtrError& vtr_error) 
 		{
-			printf("Failed to load blif file: %s\n", vtr_error.what());
-			error_code = 1;
+			printf("Odin Failed to load blif file: %s with exit code:%d \n", vtr_error.what(), ERROR_PARSE_BLIF);
+			exit(ERROR_PARSE_BLIF);
 		}
 	}
 
-	if(error_code)
-	{
-		printf("Odin Failed to read Blif with exit status: %d\n", error_code);
-		return NULL;
-	}
-
 	/* Simulate netlist */
 	if(odin_netlist && !global_args.interactive_simulation
 	&& (global_args.sim_num_test_vectors || global_args.sim_vector_input_file))
@@ -307,7 +297,7 @@ struct netlist_t_t *start_odin_ii(int argc,char **argv)
 	}
 
 	printf("--------------------------------------------------------------------\n");
-	printf("Odin ran with exit status: %d\n", error_code);
+	printf("Odin ran with exit status: %d\n", SUCCESS);
 	return odin_netlist;
 }
 
@@ -519,6 +509,12 @@ void get_options(int argc, char** argv) {
 			.default_value("true")
 			.action(argparse::Action::STORE_TRUE)
 			;
+	
+	other_sim_grp.add_argument(global_args.read_mif_input, "--read_mif")
+			.help("look for a mif file to read")
+			.default_value("false")
+			.action(argparse::Action::STORE_TRUE)
+			;
 
 	other_sim_grp.add_argument(global_args.sim_additional_pins, "-p")
 			.help("list of additional pins/nodes to monitor during simulation.\n"

ODIN_II/SRC/simulate_blif.cpp

@@ -647,8 +647,6 @@ static int is_node_ready(nnode_t* node, int cycle)
 		if (!D_pin->delay_cycle && ff_cycle < cycle)
 		{
 			D_pin->delay_cycle = true;
-			warning_message(SIMULATION_ERROR, -1, -1,
-				"%s Node %s input %s is behind by a cycle", node_name_based_on_op(node), node->name, D_pin->name);
 		}
 
 		if (ff_cycle < cycle-D_pin->delay_cycle)
@@ -670,8 +668,6 @@ static int is_node_ready(nnode_t* node, int cycle)
 				if (!pin->delay_cycle && data_cycle < cycle)
 				{
 					pin->delay_cycle = true;
-					warning_message(SIMULATION_ERROR, -1, -1,
-						"%s Node %s input %s is behind by a cycle", node_name_based_on_op(node), node->name, pin->name);
 				}
 
 				if (data_cycle < cycle-pin->delay_cycle)
@@ -2181,19 +2177,21 @@ static void instantiate_memory(nnode_t *node, int data_width, int addr_width)
 {
 	long max_address = 1 << addr_width;
 	node->memory_data = std::vector<std::vector<signed char>>(max_address, std::vector<signed char>(data_width, init_value(node)));
-	char *filename = get_mif_filename(node);
-
-	FILE *mif = fopen(filename, "r");
-	if (!mif)
-	{
-		printf("MIF %s (%dx%d) not found. \n", filename, data_width, addr_width);
-	}
-	else
+	if(global_args.read_mif_input)
 	{
-		assign_memory_from_mif_file(node, mif, filename, data_width, addr_width);
-		fclose(mif);
+		char *filename = get_mif_filename(node);
+		FILE *mif = fopen(filename, "r");
+		if (!mif)
+		{
+			printf("MIF %s (%dx%d) not found. \n", filename, data_width, addr_width);
+		}
+		else
+		{
+			assign_memory_from_mif_file(node, mif, filename, data_width, addr_width);
+			fclose(mif);
+		}
+		vtr::free(filename);
 	}
-	vtr::free(filename);
 }
 
 /*

ODIN_II/SRC/soft_logic_def_parser.cpp

@@ -33,6 +33,8 @@ OTHER DEALINGS IN THE SOFTWARE.
 
 #include "vtr_util.h"
 #include "vtr_memory.h"
+#include "vtr_path.h"
+
 #include <algorithm>
 #include <string>
 
@@ -61,12 +63,24 @@ blk_len_of_structure
 */
 std::map<std::string,soft_sub_structure*> soft_def_map;
 
-void read_soft_def_file(std::string input_file_name)
+void read_soft_def_file(t_model *hard_adder_models)
 {
-	FILE *input_file = fopen(input_file_name.c_str(),"r");
-  if(input_file)
-  {
-		printf("Reading soft_logic definition file @ %s ... ", input_file_name.c_str());
+	std::string soft_distribution(global_args.adder_def);
+	if(hard_adder_models || !global_args.adder_def || soft_distribution == "default")
+	{
+		// given any of these cases do not optimize soft logic for adders
+		return;
+	}
+
+	// use the default optimized file input
+	if(soft_distribution == "optimized")
+		soft_distribution = vtr::dirname(global_args.program_name) + "odin.soft_config";
+	//else keep as is and try to open it
+
+	FILE *input_file = fopen(soft_distribution.c_str(),"r");
+	if(input_file)
+	{
+		printf("Reading soft_logic definition file @ %s ... ", soft_distribution.c_str());
 
 		soft_def_map[std::string("+_0")] = NULL;
 		soft_def_map[std::string("/_0")] = NULL;
@@ -140,7 +154,7 @@ void read_soft_def_file(std::string input_file_name)
 		}
 		else
 			printf("DONE read %d lines\n",line_number);
-  }
+  	}
 }
 
 /*---------------------------------------------------------------------------------------------

ODIN_II/main.cpp

@@ -5,7 +5,7 @@
 int main(int argc, char **argv)
 {
 	vtr::ScopedFinishTimer t("Odin II");
-	struct netlist_t_t *odin_netlist = start_odin_ii(argc,argv);
+	struct netlist_t_t *odin_netlist = start_odin_ii(argc, argv);
 	terminate_odin_ii(odin_netlist);
 	return 0;
 

ODIN_II/regression_test/benchmark/arch/both_ram.v

@@ -0,0 +1,72 @@
+// DEFINES
+`define WIDTH 8         // Bit width 
+`define DEPTH 3         // Bit depth
+
+module  pram(
+  clock,
+  wren1,
+  wren2,
+  address,
+  address2,
+  value_in,
+  value_in2,
+  spram_out,
+  dpram_out,
+  dpram_out2,
+  dpram2_out,
+  dpram2_out2
+);
+
+// SIGNAL DECLARATIONS
+input   clock;
+
+input wren1;
+input wren2;
+
+input  [`WIDTH-1:0] value_in;
+input  [`WIDTH-1:0] value_in2;
+
+output [`WIDTH-1:0] spram_out;
+output [`WIDTH-1:0] dpram_out;
+output [`WIDTH-1:0] dpram_out2;
+output [`WIDTH-1:0] dpram2_out;
+output [`WIDTH-1:0] dpram2_out2;
+
+
+input [`DEPTH-1:0] address;
+input [`DEPTH-1:0] address2;
+
+dual_port_ram inst1(
+  .we1(wren1),
+  .we2(wren2),
+  .clk(clock),
+  .data1(value_in),
+  .data2(value_in2),
+  .out1(dpram_out),
+  .out2(dpram_out2),
+  .addr1(address),
+  .addr2(address2)
+);
+
+dual_port_ram inst2(
+  .we1(wren1),
+  .we2(1'b0),
+  .clk(clock),
+  .data1(value_in),
+  .data2(value_in2),
+  .out1(dpram2_out),
+  .out2(dpram2_out2),
+  .addr1(address),
+  .addr2(address2)
+);
+
+single_port_ram inst1(
+  .we(wren1),
+  .clk(clock),
+  .data(value_in),
+  .out(spram_out),
+  .addr(address)
+);
+
+endmodule
+