Skip to content

Commit 84e48a9

Browse files
acomodiacomodi
committed
vtr: change outstanding architectures
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent 7d55973 commit 84e48a9

File tree

3 files changed

+353
-363
lines changed

3 files changed

+353
-363
lines changed

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/k6_frac_N10_mem32K_40nm_clk_buf.xml

Lines changed: 61 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,6 @@
9191
<port name="out"/>
9292
</output_ports>
9393
</model>
94-
9594
<model name="clkbuf">
9695
<input_ports>
9796
<port name="in" combinational_sink_ports="out" is_clock="1"/>
@@ -100,7 +99,6 @@
10099
<port name="out"/>
101100
</output_ports>
102101
</model>
103-
104102
<model name="clkbufce">
105103
<input_ports>
106104
<port name="in" combinational_sink_ports="out" is_clock="1"/>
@@ -110,7 +108,6 @@
110108
<port name="out"/>
111109
</output_ports>
112110
</model>
113-
114111
<model name="single_port_ram">
115112
<input_ports>
116113
<port name="we" clock="clk"/>
@@ -153,63 +150,73 @@
153150
</model>
154151
</models>
155152
<tiles>
156-
<tile name="io" capacity="8" area="0">
157-
<equivalent_sites>
158-
<site pb_type="io"/>
159-
</equivalent_sites>
160-
<input name="outpad" num_pins="1"/>
161-
<output name="inpad" num_pins="1"/>
162-
<clock name="clock" num_pins="1"/>
163-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
164-
<pinlocations pattern="custom">
165-
<loc side="left">io.outpad io.inpad io.clock</loc>
166-
<loc side="top">io.outpad io.inpad io.clock</loc>
167-
<loc side="right">io.outpad io.inpad io.clock</loc>
168-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
169-
</pinlocations>
153+
<tile name="io" area="0">
154+
<sub_tile name="io" capacity="8">
155+
<equivalent_sites>
156+
<site pb_type="io" pin_mapping="direct"/>
157+
</equivalent_sites>
158+
<input name="outpad" num_pins="1"/>
159+
<output name="inpad" num_pins="1"/>
160+
<clock name="clock" num_pins="1"/>
161+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
162+
<pinlocations pattern="custom">
163+
<loc side="left">io.outpad io.inpad io.clock</loc>
164+
<loc side="top">io.outpad io.inpad io.clock</loc>
165+
<loc side="right">io.outpad io.inpad io.clock</loc>
166+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
167+
</pinlocations>
168+
</sub_tile>
170169
</tile>
171170
<tile name="clk_control" area="0">
172-
<equivalent_sites>
173-
<site pb_type="clk_control"/>
174-
</equivalent_sites>
175-
<input name="in" num_pins="2"/>
176-
<output name="out" num_pins="1"/>
177-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
178-
<pinlocations pattern="spread"/>
171+
<sub_tile name="clk_control">
172+
<equivalent_sites>
173+
<site pb_type="clk_control" pin_mapping="direct"/>
174+
</equivalent_sites>
175+
<input name="in" num_pins="2"/>
176+
<output name="out" num_pins="1"/>
177+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
178+
<pinlocations pattern="spread"/>
179+
</sub_tile>
179180
</tile>
180181
<tile name="clb" area="53894">
181-
<equivalent_sites>
182-
<site pb_type="clb"/>
183-
</equivalent_sites>
184-
<input name="I" num_pins="40" equivalent="full"/>
185-
<output name="O" num_pins="20" equivalent="none"/>
186-
<clock name="clk" num_pins="1"/>
187-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
188-
<pinlocations pattern="spread"/>
182+
<sub_tile name="clb">
183+
<equivalent_sites>
184+
<site pb_type="clb" pin_mapping="direct"/>
185+
</equivalent_sites>
186+
<input name="I" num_pins="40" equivalent="full"/>
187+
<output name="O" num_pins="20" equivalent="none"/>
188+
<clock name="clk" num_pins="1"/>
189+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
190+
<pinlocations pattern="spread"/>
191+
</sub_tile>
189192
</tile>
190193
<tile name="mult_36" height="4" area="396000">
191-
<equivalent_sites>
192-
<site pb_type="mult_36"/>
193-
</equivalent_sites>
194-
<input name="a" num_pins="36"/>
195-
<input name="b" num_pins="36"/>
196-
<output name="out" num_pins="72"/>
197-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
198-
<pinlocations pattern="spread"/>
194+
<sub_tile name="mult_36">
195+
<equivalent_sites>
196+
<site pb_type="mult_36" pin_mapping="direct"/>
197+
</equivalent_sites>
198+
<input name="a" num_pins="36"/>
199+
<input name="b" num_pins="36"/>
200+
<output name="out" num_pins="72"/>
201+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
202+
<pinlocations pattern="spread"/>
203+
</sub_tile>
199204
</tile>
200205
<tile name="memory" height="6" area="548000">
201-
<equivalent_sites>
202-
<site pb_type="memory"/>
203-
</equivalent_sites>
204-
<input name="addr1" num_pins="15"/>
205-
<input name="addr2" num_pins="15"/>
206-
<input name="data" num_pins="64"/>
207-
<input name="we1" num_pins="1"/>
208-
<input name="we2" num_pins="1"/>
209-
<output name="out" num_pins="64"/>
210-
<clock name="clk" num_pins="1"/>
211-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
212-
<pinlocations pattern="spread"/>
206+
<sub_tile name="memory">
207+
<equivalent_sites>
208+
<site pb_type="memory" pin_mapping="direct"/>
209+
</equivalent_sites>
210+
<input name="addr1" num_pins="15"/>
211+
<input name="addr2" num_pins="15"/>
212+
<input name="data" num_pins="64"/>
213+
<input name="we1" num_pins="1"/>
214+
<input name="we2" num_pins="1"/>
215+
<output name="out" num_pins="64"/>
216+
<clock name="clk" num_pins="1"/>
217+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
218+
<pinlocations pattern="spread"/>
219+
</sub_tile>
213220
</tile>
214221
</tiles>
215222
<!-- ODIN II specific config ends -->
@@ -328,12 +335,11 @@
328335
<power method="ignore"/>
329336
</pb_type>
330337
<!-- Define I/O pads ends -->
331-
332338
<pb_type name="clk_control">
333339
<input name="in" num_pins="2"/>
334340
<output name="out" num_pins="1"/>
335341
<mode name="clkbuf">
336-
<pb_type name="clkbuf" blif_model="clkbuf" num_pb="1">
342+
<pb_type name="clkbuf" blif_model=".subckt clkbuf" num_pb="1">
337343
<clock name="in" num_pins="1"/>
338344
<output name="out" num_pins="1"/>
339345
<delay_constant max="10e-12" in_port="clkbuf.in" out_port="clkbuf.out"/>
@@ -344,7 +350,7 @@
344350
</interconnect>
345351
</mode>
346352
<mode name="clkbufce">
347-
<pb_type name="clkbufce" blif_model="clkbufce" num_pb="1">
353+
<pb_type name="clkbufce" blif_model=".subckt clkbufce" num_pb="1">
348354
<clock name="in" num_pins="1"/>
349355
<input name="enable" num_pins="1"/>
350356
<output name="out" num_pins="1"/>

0 commit comments

Comments
 (0)