Merge branch 'master' into openfpga

Author: tangxifan

.github/workflows/test.yml

@@ -139,52 +139,68 @@ jobs:
           {
             name: 'Basic',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
-            suite: 'vtr_reg_basic'
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
+          },
+          {
+            name: 'Basic with highest assertion level',
+            params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
           },
           {
             name: 'Basic_odin',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
-            suite: 'vtr_reg_basic_odin'
+            suite: 'vtr_reg_basic_odin',
+            extra_pkgs: ""
           },
           {
             name: 'Basic with NO_GRAPHICS',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
-            suite: 'vtr_reg_basic'
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
           },
           {
             name: 'Basic with NO_SERVER',
             params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off',
-            suite: 'vtr_reg_basic'
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
           },
           {
             name: 'Basic with CAPNPROTO disabled',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off',
-            suite: 'vtr_reg_basic'
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
           },
           {
             name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
-            suite: 'vtr_reg_basic'
+            suite: 'vtr_reg_basic',
+            extra_pkgs: ""
           },
           {
             name: 'Basic_odin with VTR_ENABLE_DEBUG_LOGGING',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
-            suite: 'vtr_reg_basic_odin'
+            suite: 'vtr_reg_basic_odin',
+            extra_pkgs: ""
           },
           {
             name: 'Strong',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
-            suite: 'vtr_reg_strong'
+            suite: 'vtr_reg_strong',
+            extra_pkgs: "libeigen3-dev"
           },
           {
             name: 'Strong_odin',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
-            suite: 'vtr_reg_strong_odin'
+            suite: 'vtr_reg_strong_odin',
+            extra_pkgs: ""
           },
           {
             name: 'Valgrind Memory',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_ODIN=on',
-            suite: 'vtr_reg_valgrind_small'
+            suite: 'vtr_reg_valgrind_small',
+            extra_pkgs: ""
           }
         ]
     name: 'R: ${{ matrix.name }}'
@@ -193,10 +209,17 @@ jobs:
     - uses: actions/setup-python@v5
       with:
         python-version: 3.10.10
+
     - uses: actions/checkout@v4
       with:
         submodules: 'true'
-    - run: ./.github/scripts/install_dependencies.sh
+
+    - name: Install dependencies
+      run: ./.github/scripts/install_dependencies.sh
+
+    - name: Install external libraries
+      run: sudo apt install -y ${{ matrix.extra_pkgs }}
+      if: ${{ matrix.extra_pkgs }}
 
     - uses: hendrikmuhs/[email protected]
 

.gitignore

@@ -144,6 +144,7 @@ tags
 #
 .vscode
 .history
+.cache
 #eclipse project
 .project
 
@@ -153,4 +154,4 @@ tags
 .idea
 cmake-build-debug
 cmake-build-release
-/.metadata/
+/.metadata/

doc/src/api/vpr/rr_graph.rst

@@ -7,7 +7,7 @@ RRGraphView
 
 .. doxygenfile:: rr_graph_view.h
    :project: librrgraph
-   :sections: detaileddescription
+   :sections: briefdescription detaileddescription func prototype user-defined public-func
 
 .. doxygenclass:: RRGraphView
    :project: librrgraph
@@ -18,7 +18,7 @@ RRGraphBuilder
 
 .. doxygenfile:: rr_graph_builder.h
    :project: librrgraph
-   :sections: detaileddescription
+   :sections: briefdescription detaileddescription func prototype user-defined public-func
 
 .. doxygenclass:: RRGraphBuilder
    :project: librrgraph
@@ -29,7 +29,7 @@ RRSpatialLookup
 
 .. doxygenfile:: rr_spatial_lookup.h
    :project: librrgraph
-   :sections: detaileddescription
+   :sections: briefdescription detaileddescription func prototype user-defined public-func
 
 .. doxygenclass:: RRSpatialLookup
    :project: librrgraph

doc/src/arch/reference.rst

@@ -158,6 +158,8 @@ The valid tags within the ``<layout>`` tag are:
 
     .. note:: At most one ``<auto_layout>`` can be specified.
 
+.. _fixed_arch_grid_layout:
+
 .. arch:tag:: <fixed_layout name="string" width="int" height="int">
 
     :req_param name:

doc/src/vpr/command_line_usage.rst

@@ -82,6 +82,23 @@ VPR runs all stages of (pack, place, route, and analysis) if none of :option:`--
 
     **Default:** ``off``
 
+.. option:: --analytical_place
+
+    Run the analytical placement flow.
+    This flows uses an integrated packing and placement algorithm which uses information from the primitive level to improve clustering and placement;
+    as such, the :option:`--pack` and :option:`--place` options should not be set when this option is set.
+    This flow requires that the device has a fixed size and some of the primitive blocks are fixed somewhere on the device grid.
+
+    .. seealso:: See :ref:`Fixed FPGA Grid Layout <fixed_arch_grid_layout>` and :option:`--device` for how to fix the device size.
+
+    .. seealso:: See :ref:`VPR Placement Constraints <placement_constraints>` for how to fix primitive blocks in a design to the device grid.
+
+    .. warning::
+
+        This analytical placement flow is experimental and under active development.
+
+    **Default:** ``off``
+
 .. option:: --route
 
     Run routing stage
@@ -979,15 +996,16 @@ The following options are only valid when the placement engine is in timing-driv
 
     **Default:** ``8.0``
 
-.. option:: --place_delay_model {delta, delta_override}
+.. option:: --place_delay_model {simple, delta, delta_override}
 
     Controls how the timing-driven placer estimates delays.
 
-     * ``delta`` The router is used to profile delay from various locations in the grid for various differences in position
+     * ``simple`` The placement delay estimator is built from the router lookahead. This takes less CPU time to build and it and still as accurate as the ``delta` model.
+     * ``delta`` The router is used to profile delay from various locations in the grid for various differences in position.
      * ``delta_override`` Like ``delta`` but also includes special overrides to ensure effects of direct connects between blocks are accounted for.
        This is potentially more accurate but is more complex and depending on the architecture (e.g. number of direct connects) may increase place run-time.
 
-    **Default:** ``delta``
+    **Default:** ``simple``
 
 .. option:: --place_delay_model_reducer {min, max, median, arithmean, geomean}
 
@@ -1292,6 +1310,13 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout
     * `swns` - setup Worst Negative Slack (sWNS) [ns]
     * `stns` - Setup Total Negative Slack (sTNS) [ns]
 
+.. option:: --route_verbosity <int>
+
+    Controls the verbosity of routing output.
+    High values produce more detailed output, which can be useful for debugging or understanding the routing process.
+
+    **Default**: ``1``
+
 .. _timing_driven_router_options:
 
 Timing-Driven Router Options

libs/EXTERNAL/libcatch2

@@ -65,6 +65,9 @@ static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire
 /* Parses the number of connections type */
 static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
 
+/* Set connection from_side and to_side for custom switch block pattern*/
+static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type);
+
 /* parse switch_override in wireconn */
 static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches);
 
@@ -269,6 +272,70 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn) {
     wireconn.num_conns_formula = num_conns;
 }
 
+//set sides for a specific conn for custom switch block pattern
+static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type) {
+    if (0 == strcmp(func_type, "lt")) {
+        conn.set_sides(LEFT, TOP);
+    } else if (0 == strcmp(func_type, "lr")) {
+        conn.set_sides(LEFT, RIGHT);
+    } else if (0 == strcmp(func_type, "lb")) {
+        conn.set_sides(LEFT, BOTTOM);
+    } else if (0 == strcmp(func_type, "la")) {
+        conn.set_sides(LEFT, ABOVE);
+    } else if (0 == strcmp(func_type, "lu")) {
+        conn.set_sides(LEFT, UNDER);
+    } else if (0 == strcmp(func_type, "tl")) {
+        conn.set_sides(TOP, LEFT);
+    } else if (0 == strcmp(func_type, "tb")) {
+        conn.set_sides(TOP, BOTTOM);
+    } else if (0 == strcmp(func_type, "tr")) {
+        conn.set_sides(TOP, RIGHT);
+    } else if (0 == strcmp(func_type, "ta")) {
+        conn.set_sides(TOP, ABOVE);
+    } else if (0 == strcmp(func_type, "tu")) {
+        conn.set_sides(TOP, UNDER);
+    } else if (0 == strcmp(func_type, "rt")) {
+        conn.set_sides(RIGHT, TOP);
+    } else if (0 == strcmp(func_type, "rl")) {
+        conn.set_sides(RIGHT, LEFT);
+    } else if (0 == strcmp(func_type, "rb")) {
+        conn.set_sides(RIGHT, BOTTOM);
+    } else if (0 == strcmp(func_type, "ra")) {
+        conn.set_sides(RIGHT, ABOVE);
+    } else if (0 == strcmp(func_type, "ru")) {
+        conn.set_sides(RIGHT, UNDER);
+    } else if (0 == strcmp(func_type, "bl")) {
+        conn.set_sides(BOTTOM, LEFT);
+    } else if (0 == strcmp(func_type, "bt")) {
+        conn.set_sides(BOTTOM, TOP);
+    } else if (0 == strcmp(func_type, "br")) {
+        conn.set_sides(BOTTOM, RIGHT);
+    } else if (0 == strcmp(func_type, "ba")) {
+        conn.set_sides(BOTTOM, ABOVE);
+    } else if (0 == strcmp(func_type, "bu")) {
+        conn.set_sides(BOTTOM, UNDER);
+    } else if (0 == strcmp(func_type, "al")) {
+        conn.set_sides(ABOVE, LEFT);
+    } else if (0 == strcmp(func_type, "at")) {
+        conn.set_sides(ABOVE, TOP);
+    } else if (0 == strcmp(func_type, "ar")) {
+        conn.set_sides(ABOVE, RIGHT);
+    } else if (0 == strcmp(func_type, "ab")) {
+        conn.set_sides(ABOVE, BOTTOM);
+    } else if (0 == strcmp(func_type, "ul")) {
+        conn.set_sides(UNDER, LEFT);
+    } else if (0 == strcmp(func_type, "ut")) {
+        conn.set_sides(UNDER, TOP);
+    } else if (0 == strcmp(func_type, "ur")) {
+        conn.set_sides(UNDER, RIGHT);
+    } else if (0 == strcmp(func_type, "ub")) {
+        conn.set_sides(UNDER, BOTTOM);
+    } else {
+        /* unknown permutation function */
+        archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
+    }
+}
+
 /* Loads permutation funcs specified under Node into t_switchblock_inf. Node should be
  * <switchfuncs> */
 void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
@@ -300,34 +367,8 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu
         func_formula = get_attribute(SubElem, "formula", loc_data).as_string(nullptr);
 
         /* go through all the possible cases of func_type */
-        if (0 == strcmp(func_type, "lt")) {
-            conn.set_sides(LEFT, TOP);
-        } else if (0 == strcmp(func_type, "lr")) {
-            conn.set_sides(LEFT, RIGHT);
-        } else if (0 == strcmp(func_type, "lb")) {
-            conn.set_sides(LEFT, BOTTOM);
-        } else if (0 == strcmp(func_type, "tl")) {
-            conn.set_sides(TOP, LEFT);
-        } else if (0 == strcmp(func_type, "tb")) {
-            conn.set_sides(TOP, BOTTOM);
-        } else if (0 == strcmp(func_type, "tr")) {
-            conn.set_sides(TOP, RIGHT);
-        } else if (0 == strcmp(func_type, "rt")) {
-            conn.set_sides(RIGHT, TOP);
-        } else if (0 == strcmp(func_type, "rl")) {
-            conn.set_sides(RIGHT, LEFT);
-        } else if (0 == strcmp(func_type, "rb")) {
-            conn.set_sides(RIGHT, BOTTOM);
-        } else if (0 == strcmp(func_type, "bl")) {
-            conn.set_sides(BOTTOM, LEFT);
-        } else if (0 == strcmp(func_type, "bt")) {
-            conn.set_sides(BOTTOM, TOP);
-        } else if (0 == strcmp(func_type, "br")) {
-            conn.set_sides(BOTTOM, RIGHT);
-        } else {
-            /* unknown permutation function */
-            archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
-        }
+        set_switch_func_type(conn, func_type);
+
         func_ptr = &(sb->permutation_map[conn]);
 
         /* Here we load the specified switch function(s) */
@@ -404,8 +445,8 @@ static void check_bidir_switchblock(const t_permutation_map* permutation_map) {
     SB_Side_Connection conn;
 
     /* iterate over all combinations of from_side -> to side */
-    for (e_side from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
-        for (e_side to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
+    for (e_side from_side : TOTAL_2D_SIDES) {
+        for (e_side to_side : TOTAL_2D_SIDES) {
             /* can't connect a switchblock side to itself */
             if (from_side == to_side) {
                 continue;

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -179,10 +179,17 @@ enum e_side : unsigned char {
     RIGHT = 1,
     BOTTOM = 2,
     LEFT = 3,
-    NUM_SIDES
+    NUM_2D_SIDES = 4,
+    ABOVE = 5,
+    UNDER = 7,
+    NUM_3D_SIDES = 6,
 };
-constexpr std::array<e_side, NUM_SIDES> SIDES = {{TOP, RIGHT, BOTTOM, LEFT}};                    //Set of all side orientations
-constexpr std::array<const char*, NUM_SIDES> SIDE_STRING = {{"TOP", "RIGHT", "BOTTOM", "LEFT"}}; //String versions of side orientations
+
+constexpr std::array<e_side, NUM_2D_SIDES> TOTAL_2D_SIDES = {{TOP, RIGHT, BOTTOM, LEFT}};                     //Set of all side orientations
+constexpr std::array<const char*, NUM_2D_SIDES> TOTAL_2D_SIDE_STRINGS = {{"TOP", "RIGHT", "BOTTOM", "LEFT"}}; //String versions of side orientations
+
+constexpr std::array<e_side, NUM_3D_SIDES> TOTAL_3D_SIDES = {{TOP, RIGHT, BOTTOM, LEFT, ABOVE, UNDER}};                         //Set of all side orientations including different layers
+constexpr std::array<const char*, NUM_3D_SIDES> TOTAL_3D_SIDE_STRINGS = {{"TOP", "RIGHT", "BOTTOM", "LEFT", "ABOVE", "UNDER"}}; //String versions of side orientations including different layers
 
 /* pin location distributions */
 enum class e_pin_location_distr {
@@ -825,10 +832,11 @@ struct t_physical_pin {
 
 /**
  * @brief Describes The location of a physical tile
- * @param layer_num The die number of the physical tile. If the FPGA only has one die, or the physical tile is located
- *                  on the base die, layer_num is equal to zero. If it is one the die above base die, it is one, etc.
  * @param x The x location of the physical tile on the given die
  * @param y The y location of the physical tile on the given die
+ * @param layer_num The die number of the physical tile. If the FPGA only has one die, or the physical tile is located
+ *                  on the base die, layer_num is equal to zero. If the physical tile is location on the die immediately
+ *                  above the base die, the layer_num is 1 and so on.
  */
 struct t_physical_tile_loc {
     int x = OPEN;
@@ -1288,7 +1296,6 @@ class t_pb_graph_node {
     int total_pb_pins; /* only valid for top-level */
 
     void* temp_scratch_pad;                                     /* temporary data, useful for keeping track of things when traversing data structure */
-    t_cluster_placement_primitive* cluster_placement_primitive; /* pointer to indexing structure useful during packing stage */
 
     int* input_pin_class_size;  /* Stores the number of pins that belong to a particular input pin class */
     int num_input_pin_class;    /* number of input pin classes that this pb_graph_node has */
@@ -1978,10 +1985,12 @@ struct t_router {
 
     /** A value representing the approximate horizontal position on the FPGA device where the router
      * tile is located*/
-    double device_x_position = -1;
+    float device_x_position = -1;
     /** A value representing the approximate vertical position on the FPGA device where the router
      * tile is located*/
-    double device_y_position = -1;
+    float device_y_position = -1;
+    /** A value representing the exact layer in the FPGA device where the router tile is located.*/
+    int device_layer_position = -1;
 
     /** A list of router ids that are connected to the current router*/
     std::vector<int> connection_list;