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[Infra]: fix yosys and run_vtr_flow lint errors
Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 312504f commit 82fb973

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8 files changed

+35
-249
lines changed

8 files changed

+35
-249
lines changed

vtr_flow/benchmarks/verilog/koios/robot_rl.v

Lines changed: 6 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -11,16 +11,12 @@ Problem statement: There are 12 robots on a board with 12 regions. The aim is fo
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Q learning accelerator generated using HDL coder (Simulink / MATLAB)
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4 actions
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12 states
14-
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The design consists of 2 policy generators.
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A random number generator is used as a ploicy generator during training .(mode = 0)
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A policy generator where the action is based on the Maximum value of Q is used during inference. (mode = 1)
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2017
Misc:
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ufix6_En4 : 6 bit fixed point number --> 2 bits for integer, 4 bits for the fractional part.
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alpha = gamma = 0.5
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*/
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////////////////////////////////////////////////////////////////////////////////////////
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@@ -141,26 +137,19 @@ module Max
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wire [31:0] in0 [0:3]; // int32 [4]
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wire [31:0] Max_stage1_val [0:1]; // int32 [2]
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wire [31:0] Max_stage2_val; // int32
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assign in0[0] = in0_0;
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assign in0[1] = in0_1;
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assign in0[2] = in0_2;
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assign in0[3] = in0_3;
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// ---- Tree max implementation ----
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// ---- Tree max stage 1 ----
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assign Max_stage1_val[0] = (in0[0] >= in0[1] ? in0[0] :
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in0[1]);
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assign Max_stage1_val[1] = (in0[2] >= in0[3] ? in0[2] :
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in0[3]);
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// ---- Tree max stage 2 ----
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assign Max_stage2_val = (Max_stage1_val[0] >= Max_stage1_val[1] ? Max_stage1_val[0] :
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Max_stage1_val[1]);
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*/
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//wire [31:0] in0[0:3]; // int32 [4]
@@ -194,8 +183,8 @@ endmodule // Max
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197-
// Simpledual_port_ram_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
198-
module Simpledual_port_ram_generic
186+
// SimpleDualPortRAM_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
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module SimpleDualPortRAM_generic
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(clk,
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enb,
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wr_din,
@@ -235,7 +224,6 @@ module Simpledual_port_ram_generic
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ram[2] = 32'h00000000;
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ram[1] = 32'h00000000;
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ram[0] = 32'h00000000;
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data_int = 32'h00000000;
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end
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*/
@@ -275,7 +263,7 @@ dual_port_ram u_dual_port_ram(
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assign rd_dout = data_int;
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278-
endmodule // Simpledual_port_ram_generic
266+
endmodule // SimpleDualPortRAM_generic
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// Q_Hw: connects all the blocks and incorporates pipelining for appropriate syncing.
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module Q_HW
@@ -545,7 +533,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
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.out0(Max_out1), // int16
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.clk(clk));
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548-
Simpledual_port_ram_generic #(.AddrWidth(4),
536+
SimpleDualPortRAM_generic #(.AddrWidth(4),
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.DataWidth(32)
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)
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u_Simple_Dual_Port_RAM_System_bank3 (.clk(clk),
@@ -557,7 +545,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
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.rd_dout(pre_rd_out)
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);
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560-
Simpledual_port_ram_generic #(.AddrWidth(4),
548+
SimpleDualPortRAM_generic #(.AddrWidth(4),
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.DataWidth(32)
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)
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u_Simple_Dual_Port_RAM_System_bank2 (.clk(clk),
@@ -569,7 +557,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
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.rd_dout(pre_rd_out_1)
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);
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572-
Simpledual_port_ram_generic #(.AddrWidth(4),
560+
SimpleDualPortRAM_generic #(.AddrWidth(4),
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.DataWidth(32)
574562
)
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u_Simple_Dual_Port_RAM_System_bank1 (.clk(clk),
@@ -5090,4 +5078,3 @@ robot_high_level robot_12 ( 4'd11, clk, reset, mode, Q_12);
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endmodule
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5093-

vtr_flow/benchmarks/verilog/mcml.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18329,7 +18329,7 @@ single_port_ram sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1
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defparam cosp_replace.ADDR_WIDTH = 10;
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defparam cosp_replace.DATA_WIDTH = 32;
18332-
singlePortRam cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
18332+
single_port_ram cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
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endmodule

vtr_flow/misc/synthesis.ys

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ read_verilog -lib DDD #(DDD) will be replaced by dual_port_ram.v by python s
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read_verilog SSR #(SSR) will be replaced by spram_rename.v by python script
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read_verilog DDR #(DDR) will be replaced by dpram_rename.v by python script
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69-
69+
flatten
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# Lastly, check the hierarchy for any unknown modules,
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# and purge all modules (including blackboxes) that
7272
# aren't used

vtr_flow/misc/yosyslib/dualPortRam.v

Lines changed: 0 additions & 110 deletions
This file was deleted.

vtr_flow/misc/yosyslib/singlePortRam.v

Lines changed: 0 additions & 91 deletions
This file was deleted.

vtr_flow/scripts/python_libs/vtr/paths.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
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# ODIN paths
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odin_path = root_path / "ODIN_II"
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odin_exe_path = odin_path / "odin_II"
14-
odin_cfg_path = vtr_flow_path / "misc" / "custom_odin_config_no_mults.xml"
14+
odin_cfg_path = vtr_flow_path / "misc" / "basic_odin_config_split.xml"
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odin_verify_path = odin_path / "verify_odin.sh"
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odin_benchmark_path = odin_path / "regression_test" / "benchmark"
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odin_output_on_error_path = odin_path / "regression_test" / ".library" / "output_on_error.conf"

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