[Infra]: fix yosys and run_vtr_flow lint errors

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/benchmarks/verilog/koios/robot_rl.v

@@ -11,16 +11,12 @@ Problem statement: There are 12 robots on a board with 12 regions. The aim is fo
 Q learning accelerator generated using HDL coder (Simulink / MATLAB)
 4 actions
 12 states
-
 The design consists of 2 policy generators. 
 A random number generator is used as a ploicy generator during training .(mode = 0)
 A policy generator where the action is based on the Maximum value of Q is used during inference. (mode = 1)
-
-
 Misc: 
 ufix6_En4 : 6 bit fixed point number --> 2 bits for integer, 4 bits for the fractional part.
 alpha = gamma = 0.5
-
 */
 ////////////////////////////////////////////////////////////////////////////////////////
 
@@ -141,26 +137,19 @@ module Max
   wire  [31:0] in0 [0:3];  // int32 [4]
   wire  [31:0] Max_stage1_val [0:1];  // int32 [2]
   wire  [31:0] Max_stage2_val;  // int32
-
-
   assign in0[0] = in0_0;
   assign in0[1] = in0_1;
   assign in0[2] = in0_2;
   assign in0[3] = in0_3;
-
   // ---- Tree max implementation ----
   // ---- Tree max stage 1 ----
   assign Max_stage1_val[0] = (in0[0] >= in0[1] ? in0[0] :
               in0[1]);
   assign Max_stage1_val[1] = (in0[2] >= in0[3] ? in0[2] :
               in0[3]);
-
-
-
   // ---- Tree max stage 2 ----
   assign Max_stage2_val = (Max_stage1_val[0] >= Max_stage1_val[1] ? Max_stage1_val[0] :
               Max_stage1_val[1]);
-
 */
 
 //wire  [31:0] in0[0:3];  // int32 [4]
@@ -194,8 +183,8 @@ endmodule  // Max
 
 
 
-// Simpledual_port_ram_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
-module Simpledual_port_ram_generic
+// SimpleDualPortRAM_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
+module SimpleDualPortRAM_generic
           (clk,
            enb,
            wr_din,
@@ -235,7 +224,6 @@ module Simpledual_port_ram_generic
     ram[2] = 32'h00000000;
     ram[1] = 32'h00000000;
     ram[0] = 32'h00000000;
-
     data_int = 32'h00000000;
   end
 */
@@ -275,7 +263,7 @@ dual_port_ram u_dual_port_ram(
 
 assign rd_dout = data_int;
 
-endmodule  // Simpledual_port_ram_generic
+endmodule  // SimpleDualPortRAM_generic
 
 // Q_Hw: connects all the blocks and incorporates pipelining for appropriate syncing. 
 module Q_HW
@@ -545,7 +533,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
              .out0(Max_out1),  // int16
              .clk(clk));
 
-  Simpledual_port_ram_generic #(.AddrWidth(4),
+  SimpleDualPortRAM_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank3 (.clk(clk),
@@ -557,7 +545,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
                                                                  .rd_dout(pre_rd_out)
                                                                  );
 
-  Simpledual_port_ram_generic #(.AddrWidth(4),
+  SimpleDualPortRAM_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank2 (.clk(clk),
@@ -569,7 +557,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
                                                                  .rd_dout(pre_rd_out_1)
                                                                  );
 
-  Simpledual_port_ram_generic #(.AddrWidth(4),
+  SimpleDualPortRAM_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank1 (.clk(clk),
@@ -5090,4 +5078,3 @@ robot_high_level robot_12 ( 4'd11, clk, reset, mode, Q_12);
 endmodule
 
 
-

vtr_flow/benchmarks/verilog/mcml.v

@@ -18329,7 +18329,7 @@ single_port_ram sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1
 
 defparam cosp_replace.ADDR_WIDTH = 10;
 defparam cosp_replace.DATA_WIDTH = 32;
-singlePortRam cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
+single_port_ram cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
 
 
 endmodule

vtr_flow/misc/synthesis.ys

@@ -66,7 +66,7 @@ read_verilog -lib DDD     #(DDD) will be replaced by dual_port_ram.v by python s
 read_verilog SSR         #(SSR) will be replaced by spram_rename.v by python script
 read_verilog DDR         #(DDR) will be replaced by dpram_rename.v by python script
 
-
+flatten
 # Lastly, check the hierarchy for any unknown modules,
 # and purge all modules (including blackboxes) that
 # aren't used

vtr_flow/misc/yosyslib/dualPortRam.v

@@ -11,7 +11,7 @@
 # ODIN paths
 odin_path = root_path / "ODIN_II"
 odin_exe_path = odin_path / "odin_II"
-odin_cfg_path = vtr_flow_path / "misc" / "custom_odin_config_no_mults.xml"
+odin_cfg_path = vtr_flow_path / "misc" / "basic_odin_config_split.xml"
 odin_verify_path = odin_path / "verify_odin.sh"
 odin_benchmark_path = odin_path / "regression_test" / "benchmark"
 odin_output_on_error_path = odin_path / "regression_test" / ".library" / "output_on_error.conf"