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acomodiacomodi
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equivalent: updated regression test (WIP)
Signed-off-by: Alessandro Comodi <[email protected]>
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‎vtr_flow/arch/equivalent_sites/equivalent.xml

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<!-- This architecture definition represents a simplified version of a SLICEM site -->
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<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
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<models>
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<model name="IO_0">
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<input_ports>
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<port name="I" combinational_sink_ports="O"/>
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</input_ports>
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<output_ports>
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<port name="O"/>
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</output_ports>
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</model>
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<model name="IO_1">
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<input_ports>
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<port name="I" combinational_sink_ports="O"/>
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</input_ports>
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<output_ports>
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<port name="O"/>
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</output_ports>
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</model>
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<model name="IO_2">
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<input_ports>
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<port name="I" combinational_sink_ports="O"/>
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</input_ports>
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<output_ports>
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<port name="O"/>
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</output_ports>
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</model>
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<model name="IO_3">
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<input_ports>
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<port name="I" combinational_sink_ports="O"/>
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</input_ports>
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<output_ports>
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<port name="O"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io_tile">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<equivalent_sites>
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<site pb_type="io_site_0">
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<direct from="io_tile.I" to="io_site_0.I"/>
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<direct from="io_tile.O" to="io_site_0.O"/>
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</site>
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<site pb_type="io_site_1">
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<direct from="io_tile.I" to="io_site_1.I"/>
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<direct from="io_tile.O" to="io_site_1.O"/>
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</site>
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<site pb_type="io_site_2">
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<direct from="io_tile.I" to="io_site_2.I"/>
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<direct from="io_tile.O" to="io_site_2.O"/>
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</site>
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<site pb_type="io_site_3">
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<direct from="io_tile.I" to="io_site_3.I"/>
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<direct from="io_tile.O" to="io_site_3.O"/>
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</site>
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</equivalent_sites>
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<pinlocations pattern="custom">
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<loc side="top" xoffset="0" yoffset="0">io_tile.I io_tile.O</loc>
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<loc side="left" xoffset="0" yoffset="0">io_tile.I io_tile.O</loc>
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<loc side="bottom" xoffset="0" yoffset="0">io_tile.I io_tile.O</loc>
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<loc side="right" xoffset="0" yoffset="0">io_tile.I io_tile.O</loc>
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</pinlocations>
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<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
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</tile>
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</tiles>
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<complexblocklist>
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<pb_type name="io_site_0">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<mode name="INOUT">
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<pb_type blif_model=".subckt IO_0" name="io_0" num_pb="1">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<delay_constant max="1.667e-9" in_port="io_0.I" out_port="io_0.O"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_0.I" name="i_0" output="io_0.I"/>
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<direct input="io_0.O" name="o_0" output="io_site_0.O"/>
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</interconnect>
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</mode>
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<mode name="IN">
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<pb_type blif_model=".input" name="input_0" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="input_0.inpad" name="i_0" output="io_site_0.O"/>
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</interconnect>
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</mode>
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<mode name="OUT">
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<pb_type blif_model=".output" name="output_0" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_0.I" name="o_0" output="output_0.outpad"/>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="io_site_1">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<mode name="INOUT">
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<pb_type blif_model=".subckt IO_1" name="io_1" num_pb="1">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<delay_constant max="1.667e-9" in_port="io_1.I" out_port="io_1.O"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_1.I" name="i_1" output="io_1.I"/>
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<direct input="io_1.O" name="o_1" output="io_site_1.O"/>
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</interconnect>
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</mode>
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<mode name="IN">
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<pb_type blif_model=".input" name="input_1" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="input_1.inpad" name="i_1" output="io_site_1.O"/>
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</interconnect>
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</mode>
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<mode name="OUT">
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<pb_type blif_model=".output" name="output_1" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_1.I" name="o_1" output="output_1.outpad"/>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="io_site_2">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<mode name="INOUT">
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<pb_type blif_model=".subckt IO_2" name="io_2" num_pb="1">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<delay_constant max="1.667e-9" in_port="io_2.I" out_port="io_2.O"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_2.I" name="i_2" output="io_2.I"/>
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<direct input="io_2.O" name="o_2" output="io_site_2.O"/>
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</interconnect>
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</mode>
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<mode name="IN">
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<pb_type blif_model=".input" name="input_2" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="input_2.inpad" name="i_2" output="io_site_2.O"/>
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</interconnect>
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</mode>
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<mode name="OUT">
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<pb_type blif_model=".output" name="output_2" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_2.I" name="o_2" output="output_2.outpad"/>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="io_site_3">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<mode name="INOUT">
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<pb_type blif_model=".subckt IO_3" name="io_3" num_pb="1">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<delay_constant max="1.667e-9" in_port="io_3.I" out_port="io_3.O"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_3.I" name="i_3" output="io_3.I"/>
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<direct input="io_3.O" name="o_3" output="io_site_3.O"/>
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</interconnect>
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</mode>
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<mode name="IN">
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<pb_type blif_model=".input" name="input_3" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="input_3.inpad" name="i_3" output="io_site_3.O"/>
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</interconnect>
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</mode>
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<mode name="OUT">
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<pb_type blif_model=".output" name="output_3" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct input="io_site_3.I" name="o_3" output="output_3.outpad"/>
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</interconnect>
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</mode>
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</pb_type>
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</complexblocklist>
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<layout>
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<fixed_layout name="TEST" width="4" height="4">
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<single priority="1" type="io_tile" x="0" y="0"/>
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<single priority="1" type="io_tile" x="0" y="1"/>
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<single priority="1" type="io_tile" x="0" y="2"/>
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<single priority="1" type="io_tile" x="0" y="3"/>
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<single priority="1" type="io_tile" x="1" y="0"/>
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<single priority="1" type="io_tile" x="1" y="1"/>
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<single priority="1" type="io_tile" x="1" y="2"/>
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<single priority="1" type="io_tile" x="1" y="3"/>
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<single priority="1" type="io_tile" x="2" y="0"/>
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<single priority="1" type="io_tile" x="2" y="1"/>
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<single priority="1" type="io_tile" x="2" y="2"/>
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<single priority="1" type="io_tile" x="2" y="3"/>
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<single priority="1" type="io_tile" x="3" y="0"/>
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<single priority="1" type="io_tile" x="3" y="1"/>
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<single priority="1" type="io_tile" x="3" y="2"/>
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<single priority="1" type="io_tile" x="3" y="3"/>
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</fixed_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
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<area grid_logic_tile_area="14813.392"/>
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<connection_block input_switch_name="buffer"/>
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<switch_block fs="3" type="wilton"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.0"/>
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<y distr="uniform" peak="1.0"/>
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</chan_width_distr>
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</device>
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<switchlist>
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<switch Cin=".77e-15" Cout="4e-15" R="551" Tdel="6.8e-12" buf_size="27.645901" mux_trans_size="2.630740" name="routing" type="mux"/>
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<switch Cin=".77e-15" Cout="4e-15" R="551" Tdel="6.8e-12" buf_size="27.645901" mux_trans_size="2.630740" name="buffer" type="mux"/>
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</switchlist>
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<segmentlist>
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<segment Cmetal="22.5e-15" Rmetal="101" freq="1.0" length="12" name="dummy" type="bidir">
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<wire_switch name="routing"/>
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<opin_switch name="routing"/>
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<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1</cb>
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</segment>
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</segmentlist>
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</architecture>

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