Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into placement_search_range

Author: amin1377

.github/workflows/nightly_test_manual.yml

@@ -112,4 +112,5 @@ jobs:
         name: nightly_test_results
         path: |
           vtr_flow/**/*.log
+          vtr_flow/**/vpr.out
           vtr_flow/**/parse_results*.txt

.github/workflows/test.yml

@@ -99,7 +99,7 @@ jobs:
       run: ./dev/${{ matrix.script }}
 
 
-  UniTests:
+  UnitTests:
     name: 'U: C++ Unit Tests'
     runs-on: ubuntu-24.04
     steps:
@@ -125,6 +125,92 @@ jobs:
       run: ./.github/scripts/unittest.sh
 
 
+  # This test builds different variations of VTR (with different CMake Params)
+  # and ensures that they can run the basic regression tests. This also ensures
+  # that these build variations are warning clean.
+  BuildVariations:
+    runs-on: ubuntu-24.04
+    name: 'B: Build Variations'
+    env:
+      # For the CI, we want all build variations to be warning clean.
+      # NOTE: Need to turn IPO off due to false warnings being produced.
+      COMMON_CMAKE_PARAMS: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off'
+    steps:
+
+    - uses: actions/setup-python@v5
+      with:
+        python-version: 3.12.3
+
+    - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
+
+    - name: 'Get number of CPU cores'
+      uses: SimenB/github-actions-cpu-cores@v2
+      id: cpu-cores
+
+    - name: 'Install dependencies'
+      run: ./.github/scripts/install_dependencies.sh
+
+    - name: 'ccache'
+      uses: hendrikmuhs/[email protected]
+
+    - name: 'Test with VTR_ASSERT_LEVEL 4'
+      if: success() || failure()
+      env:
+        CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ASSERT_LEVEL=4"
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        rm -f build/CMakeCache.txt
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        make -j${{ steps.cpu-cores.outputs.count}}
+        ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
+
+    - name: 'Test with NO_GRAPHICS'
+      if: success() || failure()
+      env:
+        CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_EZGL=off"
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        rm -f build/CMakeCache.txt
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        make -j${{ steps.cpu-cores.outputs.count}}
+        ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
+
+    - name: 'Test with NO_SERVER'
+      if: success() || failure()
+      env:
+        CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_SERVER=off"
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        rm -f build/CMakeCache.txt
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        make -j${{ steps.cpu-cores.outputs.count}}
+        ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
+
+    - name: 'Test with CAPNPROTO disabled'
+      if: success() || failure()
+      env:
+        CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_CAPNPROTO=off"
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        rm -f build/CMakeCache.txt
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        make -j${{ steps.cpu-cores.outputs.count}}
+        ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
+
+    - name: 'Test with serial VPR_EXECUTION_ENGINE'
+      if: success() || failure()
+      env:
+        CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial"
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        rm -f build/CMakeCache.txt
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        make -j${{ steps.cpu-cores.outputs.count}}
+        ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
+
+
   Regression:
     runs-on: ubuntu-24.04
     strategy:
@@ -137,42 +223,12 @@ jobs:
             suite: 'vtr_reg_basic',
             extra_pkgs: ""
           },
-          {
-            name: 'Basic with highest assertion level',
-            params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
-            suite: 'vtr_reg_basic',
-            extra_pkgs: ""
-          },
           {
             name: 'Basic_odin',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
             suite: 'vtr_reg_basic_odin',
             extra_pkgs: ""
           },
-          {
-            name: 'Basic with NO_GRAPHICS',
-            params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
-            suite: 'vtr_reg_basic',
-            extra_pkgs: ""
-          },
-          {
-            name: 'Basic with NO_SERVER',
-            params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off',
-            suite: 'vtr_reg_basic',
-            extra_pkgs: ""
-          },
-          {
-            name: 'Basic with CAPNPROTO disabled',
-            params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off',
-            suite: 'vtr_reg_basic',
-            extra_pkgs: ""
-          },
-          {
-            name: 'Basic with serial VPR_EXECUTION_ENGINE',
-            params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial',
-            suite: 'vtr_reg_basic',
-            extra_pkgs: ""
-          },
           {
             name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
             params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
@@ -484,7 +540,8 @@ jobs:
     needs:
       - Build
       - Format
-      - UniTests
+      - UnitTests
+      - BuildVariations
       - Regression
       - Sanitized
       - Parmys

doc/src/vpr/command_line_usage.rst

@@ -1336,6 +1336,15 @@ Analytical Placement is generally split into three stages:
 
     **Default:** ``1``
 
+.. option:: --ap_generate_mass_report {on | off}
+
+    Controls whether to generate a report on how the partial legalizer
+    within the AP flow calculates the mass of primitives and the
+    capacity of tiles on the device. This report is useful when
+    debugging the partial legalizer.
+
+    **Default:** ``off``
+
 
 .. _router_options:
 

libs/libarchfpga/src/arch_check.cpp

@@ -1,5 +1,7 @@
 #include <set>
+#include <sstream>
 
+#include "arch_util.h"
 #include "logic_types.h"
 #include "vtr_log.h"
 #include "arch_error.h"

libs/libarchfpga/src/arch_check.h

@@ -1,5 +1,4 @@
-#ifndef ARCH_CHECK_H
-#define ARCH_CHECK_H
+#pragma once
 
 /**
  *  This file includes all the definitions of functions which purpose is to
@@ -8,12 +7,9 @@
  *  All new functions corresponding to the architecture checking should end up here.
  */
 
-#include "arch_types.h"
-#include "arch_util.h"
-
-#include "physical_types_util.h"
-
-#include "vtr_util.h"
+#include <stdint.h>
+#include "logic_types.h"
+#include "physical_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -76,5 +72,3 @@ void check_models(t_arch* arch);
 #ifdef __cplusplus
 }
 #endif
-
-#endif

libs/libarchfpga/src/arch_error.h

@@ -1,5 +1,4 @@
-#ifndef ARCH_ERROR_H
-#define ARCH_ERROR_H
+#pragma once
 
 #include "vtr_error.h"
 #include <cstdarg>
@@ -14,5 +13,3 @@ class ArchFpgaError : public vtr::VtrError {
     ArchFpgaError(std::string msg = "", std::string new_filename = "", size_t new_linenumber = -1)
         : vtr::VtrError(msg, new_filename, new_linenumber) {}
 };
-
-#endif

libs/libarchfpga/src/arch_types.h

@@ -1,17 +1,11 @@
+#pragma once
 /*
  * Data types describing the FPGA architecture.
  *
  * Date: February 19, 2009
  * Authors: Jason Luu and Kenneth Kent
  */
 
-#ifndef ARCH_TYPES_H
-#define ARCH_TYPES_H
-
-#include "logic_types.h"
-#include "physical_types.h"
-#include "cad_types.h"
-
 /* Input file parsing. */
 #define TOKENS " \t\n"
 
@@ -25,5 +19,3 @@ enum class e_arch_format {
     VTR,            ///<VTR-specific device XML format
     FPGAInterchange ///<FPGA Interchange device format
 };
-
-#endif

libs/libarchfpga/src/arch_util.h

@@ -1,7 +1,5 @@
-#ifndef ARCH_UTIL_H
-#define ARCH_UTIL_H
+#pragma once
 
-#include <regex>
 #include <unordered_set>
 #include "physical_types.h"
 
@@ -114,4 +112,3 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
                                  std::vector<t_logical_block_type>& LogicalBlockTypes);
 
 void setup_pin_classes(t_physical_tile_type* type);
-#endif

libs/libarchfpga/src/cad_types.h

@@ -1,10 +1,8 @@
+#pragma once
 /*
  * Data types used to give architectural hints for the CAD algorithm
  */
-#ifndef CAD_TYPES_H
-#define CAD_TYPES_H
 
-#include "logic_types.h"
 #include "physical_types.h"
 
 struct t_pack_pattern_connections;
@@ -128,5 +126,3 @@ struct t_cluster_placement_primitive {
     float base_cost;        /* cost independent of current status of packing */
     float incremental_cost; /* cost dependent on current status of packing */
 };
-
-#endif

libs/libarchfpga/src/clock_types.h

@@ -1,8 +1,6 @@
-#ifndef CLOCK_TYPES_H
-#define CLOCK_TYPES_H
+#pragma once
 
 #include <string>
-#include <vector>
 
 enum class e_clock_type {
     SPINE,
@@ -59,5 +57,3 @@ struct t_clock_connection_arch {
     std::string locationy;
     float fc;
 };
-
-#endif

libs/libarchfpga/src/device_grid.h

@@ -1,5 +1,4 @@
-#ifndef DEVICE_GRID
-#define DEVICE_GRID
+#pragma once
 
 #include <string>
 #include <vector>
@@ -149,5 +148,3 @@ class DeviceGrid {
 
     std::vector<t_logical_block_type_ptr> limiting_resources_;
 };
-
-#endif

libs/libarchfpga/src/echo_arch.h

@@ -1,11 +1,9 @@
-#ifndef ECHO_ARCH_H
-#define ECHO_ARCH_H
+#pragma once
 
-#include "arch_types.h"
+#include <vector>
+#include "physical_types.h"
 
 void EchoArch(const char* EchoFile,
               const std::vector<t_physical_tile_type>& PhysicalTileTypes,
               const std::vector<t_logical_block_type>& LogicalBlockTypes,
               const t_arch* arch);
-
-#endif

libs/libarchfpga/src/histogram.cpp

@@ -1,6 +1,5 @@
 #include <algorithm>
 #include <string>
-#include <sstream>
 #include <cmath>
 
 #include "vtr_log.h"

libs/libarchfpga/src/histogram.h

@@ -1,7 +1,7 @@
-#ifndef VPR_HISTOGRAM_H
-#define VPR_HISTOGRAM_H
+#pragma once
 
 #include <limits>
+#include <string>
 #include <vector>
 
 struct HistogramBucket {
@@ -22,5 +22,3 @@ void print_histogram(std::vector<HistogramBucket> histogram);
 float get_histogram_mode(std::vector<HistogramBucket> histogram);
 
 std::vector<std::string> format_histogram(std::vector<HistogramBucket> histogram, size_t width = 80);
-
-#endif

libs/libarchfpga/src/logic_types.cpp

@@ -28,6 +28,7 @@ LogicalModels::LogicalModels() {
     //INPAD
     {
         LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT);
+        VTR_ASSERT_OPT(inpad_model_id == MODEL_INPUT_ID);
         t_model& inpad_model = get_model(inpad_model_id);
 
         inpad_model.inputs = nullptr;
@@ -47,6 +48,7 @@ LogicalModels::LogicalModels() {
     //OUTPAD
     {
         LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT);
+        VTR_ASSERT_OPT(outpad_model_id == MODEL_OUTPUT_ID);
         t_model& outpad_model = get_model(outpad_model_id);
 
         outpad_model.inputs = new t_model_ports;
@@ -66,6 +68,7 @@ LogicalModels::LogicalModels() {
     //LATCH
     {
         LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH);
+        VTR_ASSERT_OPT(latch_model_id == MODEL_LATCH_ID);
         t_model& latch_model = get_model(latch_model_id);
         t_model_ports* latch_model_input_port_1 = new t_model_ports;
         t_model_ports* latch_model_input_port_2 = new t_model_ports;
@@ -104,6 +107,7 @@ LogicalModels::LogicalModels() {
     //NAMES
     {
         LogicalModelId names_model_id = create_logical_model(MODEL_NAMES);
+        VTR_ASSERT_OPT(names_model_id == MODEL_NAMES_ID);
         t_model& names_model = get_model(names_model_id);
 
         names_model.inputs = new t_model_ports;