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Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into placement_search_range
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.github/workflows/nightly_test_manual.yml

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@@ -112,4 +112,5 @@ jobs:
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name: nightly_test_results
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path: |
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vtr_flow/**/*.log
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vtr_flow/**/vpr.out
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vtr_flow/**/parse_results*.txt

.github/workflows/test.yml

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@@ -99,7 +99,7 @@ jobs:
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run: ./dev/${{ matrix.script }}
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UniTests:
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UnitTests:
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name: 'U: C++ Unit Tests'
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runs-on: ubuntu-24.04
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steps:
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run: ./.github/scripts/unittest.sh
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# This test builds different variations of VTR (with different CMake Params)
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# and ensures that they can run the basic regression tests. This also ensures
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# that these build variations are warning clean.
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BuildVariations:
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runs-on: ubuntu-24.04
133+
name: 'B: Build Variations'
134+
env:
135+
# For the CI, we want all build variations to be warning clean.
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# NOTE: Need to turn IPO off due to false warnings being produced.
137+
COMMON_CMAKE_PARAMS: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off'
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steps:
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- uses: actions/setup-python@v5
141+
with:
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python-version: 3.12.3
143+
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- uses: actions/checkout@v4
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with:
146+
submodules: 'true'
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- name: 'Get number of CPU cores'
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uses: SimenB/github-actions-cpu-cores@v2
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id: cpu-cores
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- name: 'Install dependencies'
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run: ./.github/scripts/install_dependencies.sh
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- name: 'ccache'
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uses: hendrikmuhs/[email protected]
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- name: 'Test with VTR_ASSERT_LEVEL 4'
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if: success() || failure()
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env:
161+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ASSERT_LEVEL=4"
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NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
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run: |
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rm -f build/CMakeCache.txt
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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make -j${{ steps.cpu-cores.outputs.count}}
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./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
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- name: 'Test with NO_GRAPHICS'
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if: success() || failure()
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env:
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CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_EZGL=off"
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NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
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run: |
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rm -f build/CMakeCache.txt
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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make -j${{ steps.cpu-cores.outputs.count}}
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./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
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- name: 'Test with NO_SERVER'
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if: success() || failure()
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env:
183+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_SERVER=off"
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NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
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run: |
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rm -f build/CMakeCache.txt
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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make -j${{ steps.cpu-cores.outputs.count}}
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./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
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- name: 'Test with CAPNPROTO disabled'
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if: success() || failure()
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env:
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CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_CAPNPROTO=off"
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NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
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run: |
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rm -f build/CMakeCache.txt
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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make -j${{ steps.cpu-cores.outputs.count}}
200+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
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202+
- name: 'Test with serial VPR_EXECUTION_ENGINE'
203+
if: success() || failure()
204+
env:
205+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial"
206+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
207+
run: |
208+
rm -f build/CMakeCache.txt
209+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
210+
make -j${{ steps.cpu-cores.outputs.count}}
211+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
212+
213+
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Regression:
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runs-on: ubuntu-24.04
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strategy:
@@ -137,42 +223,12 @@ jobs:
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suite: 'vtr_reg_basic',
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extra_pkgs: ""
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},
140-
{
141-
name: 'Basic with highest assertion level',
142-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
143-
suite: 'vtr_reg_basic',
144-
extra_pkgs: ""
145-
},
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{
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name: 'Basic_odin',
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params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
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suite: 'vtr_reg_basic_odin',
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extra_pkgs: ""
151231
},
152-
{
153-
name: 'Basic with NO_GRAPHICS',
154-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
155-
suite: 'vtr_reg_basic',
156-
extra_pkgs: ""
157-
},
158-
{
159-
name: 'Basic with NO_SERVER',
160-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off',
161-
suite: 'vtr_reg_basic',
162-
extra_pkgs: ""
163-
},
164-
{
165-
name: 'Basic with CAPNPROTO disabled',
166-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off',
167-
suite: 'vtr_reg_basic',
168-
extra_pkgs: ""
169-
},
170-
{
171-
name: 'Basic with serial VPR_EXECUTION_ENGINE',
172-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial',
173-
suite: 'vtr_reg_basic',
174-
extra_pkgs: ""
175-
},
176232
{
177233
name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
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params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
@@ -484,7 +540,8 @@ jobs:
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needs:
485541
- Build
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- Format
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- UniTests
543+
- UnitTests
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- BuildVariations
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- Regression
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- Sanitized
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- Parmys

doc/src/vpr/command_line_usage.rst

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@@ -1336,6 +1336,15 @@ Analytical Placement is generally split into three stages:
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13371337
**Default:** ``1``
13381338

1339+
.. option:: --ap_generate_mass_report {on | off}
1340+
1341+
Controls whether to generate a report on how the partial legalizer
1342+
within the AP flow calculates the mass of primitives and the
1343+
capacity of tiles on the device. This report is useful when
1344+
debugging the partial legalizer.
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**Default:** ``off``
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.. _router_options:
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libs/libarchfpga/src/arch_check.cpp

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#include <set>
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#include <sstream>
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#include "arch_util.h"
35
#include "logic_types.h"
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#include "vtr_log.h"
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#include "arch_error.h"

libs/libarchfpga/src/arch_check.h

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1-
#ifndef ARCH_CHECK_H
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#define ARCH_CHECK_H
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#pragma once
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/**
54
* This file includes all the definitions of functions which purpose is to
@@ -8,12 +7,9 @@
87
* All new functions corresponding to the architecture checking should end up here.
98
*/
109

11-
#include "arch_types.h"
12-
#include "arch_util.h"
13-
14-
#include "physical_types_util.h"
15-
16-
#include "vtr_util.h"
10+
#include <stdint.h>
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#include "logic_types.h"
12+
#include "physical_types.h"
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1814
#ifdef __cplusplus
1915
extern "C" {
@@ -76,5 +72,3 @@ void check_models(t_arch* arch);
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#ifdef __cplusplus
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}
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#endif
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#endif

libs/libarchfpga/src/arch_error.h

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#ifndef ARCH_ERROR_H
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#define ARCH_ERROR_H
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#pragma once
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#include "vtr_error.h"
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#include <cstdarg>
@@ -14,5 +13,3 @@ class ArchFpgaError : public vtr::VtrError {
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ArchFpgaError(std::string msg = "", std::string new_filename = "", size_t new_linenumber = -1)
1514
: vtr::VtrError(msg, new_filename, new_linenumber) {}
1615
};
17-
18-
#endif

libs/libarchfpga/src/arch_types.h

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1+
#pragma once
12
/*
23
* Data types describing the FPGA architecture.
34
*
45
* Date: February 19, 2009
56
* Authors: Jason Luu and Kenneth Kent
67
*/
78

8-
#ifndef ARCH_TYPES_H
9-
#define ARCH_TYPES_H
10-
11-
#include "logic_types.h"
12-
#include "physical_types.h"
13-
#include "cad_types.h"
14-
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/* Input file parsing. */
1610
#define TOKENS " \t\n"
1711

@@ -25,5 +19,3 @@ enum class e_arch_format {
2519
VTR, ///<VTR-specific device XML format
2620
FPGAInterchange ///<FPGA Interchange device format
2721
};
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29-
#endif

libs/libarchfpga/src/arch_util.h

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#ifndef ARCH_UTIL_H
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#define ARCH_UTIL_H
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#pragma once
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#include <regex>
53
#include <unordered_set>
64
#include "physical_types.h"
75

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114112
std::vector<t_logical_block_type>& LogicalBlockTypes);
115113

116114
void setup_pin_classes(t_physical_tile_type* type);
117-
#endif

libs/libarchfpga/src/cad_types.h

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1+
#pragma once
12
/*
23
* Data types used to give architectural hints for the CAD algorithm
34
*/
4-
#ifndef CAD_TYPES_H
5-
#define CAD_TYPES_H
65

7-
#include "logic_types.h"
86
#include "physical_types.h"
97

108
struct t_pack_pattern_connections;
@@ -128,5 +126,3 @@ struct t_cluster_placement_primitive {
128126
float base_cost; /* cost independent of current status of packing */
129127
float incremental_cost; /* cost dependent on current status of packing */
130128
};
131-
132-
#endif

libs/libarchfpga/src/clock_types.h

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1-
#ifndef CLOCK_TYPES_H
2-
#define CLOCK_TYPES_H
1+
#pragma once
32

43
#include <string>
5-
#include <vector>
64

75
enum class e_clock_type {
86
SPINE,
@@ -59,5 +57,3 @@ struct t_clock_connection_arch {
5957
std::string locationy;
6058
float fc;
6159
};
62-
63-
#endif

libs/libarchfpga/src/device_grid.h

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#ifndef DEVICE_GRID
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#define DEVICE_GRID
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#pragma once
32

43
#include <string>
54
#include <vector>
@@ -149,5 +148,3 @@ class DeviceGrid {
149148

150149
std::vector<t_logical_block_type_ptr> limiting_resources_;
151150
};
152-
153-
#endif

libs/libarchfpga/src/echo_arch.h

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1-
#ifndef ECHO_ARCH_H
2-
#define ECHO_ARCH_H
1+
#pragma once
32

4-
#include "arch_types.h"
3+
#include <vector>
4+
#include "physical_types.h"
55

66
void EchoArch(const char* EchoFile,
77
const std::vector<t_physical_tile_type>& PhysicalTileTypes,
88
const std::vector<t_logical_block_type>& LogicalBlockTypes,
99
const t_arch* arch);
10-
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#endif

libs/libarchfpga/src/histogram.cpp

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#include <algorithm>
22
#include <string>
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#include <sstream>
43
#include <cmath>
54

65
#include "vtr_log.h"

libs/libarchfpga/src/histogram.h

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1-
#ifndef VPR_HISTOGRAM_H
2-
#define VPR_HISTOGRAM_H
1+
#pragma once
32

43
#include <limits>
4+
#include <string>
55
#include <vector>
66

77
struct HistogramBucket {
@@ -22,5 +22,3 @@ void print_histogram(std::vector<HistogramBucket> histogram);
2222
float get_histogram_mode(std::vector<HistogramBucket> histogram);
2323

2424
std::vector<std::string> format_histogram(std::vector<HistogramBucket> histogram, size_t width = 80);
25-
26-
#endif

libs/libarchfpga/src/logic_types.cpp

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@@ -28,6 +28,7 @@ LogicalModels::LogicalModels() {
2828
//INPAD
2929
{
3030
LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT);
31+
VTR_ASSERT_OPT(inpad_model_id == MODEL_INPUT_ID);
3132
t_model& inpad_model = get_model(inpad_model_id);
3233

3334
inpad_model.inputs = nullptr;
@@ -47,6 +48,7 @@ LogicalModels::LogicalModels() {
4748
//OUTPAD
4849
{
4950
LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT);
51+
VTR_ASSERT_OPT(outpad_model_id == MODEL_OUTPUT_ID);
5052
t_model& outpad_model = get_model(outpad_model_id);
5153

5254
outpad_model.inputs = new t_model_ports;
@@ -66,6 +68,7 @@ LogicalModels::LogicalModels() {
6668
//LATCH
6769
{
6870
LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH);
71+
VTR_ASSERT_OPT(latch_model_id == MODEL_LATCH_ID);
6972
t_model& latch_model = get_model(latch_model_id);
7073
t_model_ports* latch_model_input_port_1 = new t_model_ports;
7174
t_model_ports* latch_model_input_port_2 = new t_model_ports;
@@ -104,6 +107,7 @@ LogicalModels::LogicalModels() {
104107
//NAMES
105108
{
106109
LogicalModelId names_model_id = create_logical_model(MODEL_NAMES);
110+
VTR_ASSERT_OPT(names_model_id == MODEL_NAMES_ID);
107111
t_model& names_model = get_model(names_model_id);
108112

109113
names_model.inputs = new t_model_ports;

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