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Merge branch 'master' into fix_cluster_constraints_init
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# Format: //devtools/kokoro/config/proto/build.proto
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build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
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# 12 hours
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timeout_mins: 720
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action {
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define_artifacts {
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# File types
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regex: "**/*.out"
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regex: "**/vpr_stdout.log"
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regex: "**/parse_results.txt"
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regex: "**/qor_results.txt"
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regex: "**/pack.log"
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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}
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env_vars {
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key: "KOKORO_TYPE"
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value: "continuous"
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}
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env_vars {
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key: "KOKORO_DIR"
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value: "vtr-verilog-to-routing"
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}
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env_vars {
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key: "VTR_DIR"
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value: "vtr-verilog-to-routing"
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}
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#Use default build configuration
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env_vars {
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key: "VTR_CMAKE_PARAMS"
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value: ""
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}
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env_vars {
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key: "VTR_TEST"
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value: "odin_reg_strong"
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}
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#Options for run_reg_test.py
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# -show_failures: show tool failures in main log output
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env_vars {
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key: "VTR_TEST_OPTIONS"
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value: "-show_failures"
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}
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env_vars {
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key: "NUM_CORES"
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value: "3"
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}
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# Format: //devtools/kokoro/config/proto/build.proto
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build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
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# 12 hours
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timeout_mins: 720
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action {
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define_artifacts {
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# File types
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regex: "**/*.out"
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regex: "**/vpr_stdout.log"
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regex: "**/parse_results.txt"
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regex: "**/qor_results.txt"
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regex: "**/pack.log"
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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}
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env_vars {
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key: "KOKORO_TYPE"
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value: "presubmit"
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}
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env_vars {
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key: "KOKORO_DIR"
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value: "vtr-verilog-to-routing"
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}
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env_vars {
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key: "VTR_DIR"
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value: "vtr-verilog-to-routing"
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}
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#Use default build configuration
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env_vars {
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key: "VTR_CMAKE_PARAMS"
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value: ""
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}
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env_vars {
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key: "VTR_TEST"
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value: "odin_reg_strong"
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}
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#Options for run_reg_test.py
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# -show_failures: show tool failures in main log output
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env_vars {
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key: "VTR_TEST_OPTIONS"
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value: "-show_failures"
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}
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env_vars {
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key: "NUM_CORES"
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value: "3"
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}

.github/kokoro/run-vtr.sh

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ source $SCRIPT_DIR/steps/hostinfo.sh
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# Output git information
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source $SCRIPT_DIR/steps/git.sh
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19-
if [ $VTR_TEST == "vtr_reg_strong" ]; then
19+
if [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ]; then
2020
source $SCRIPT_DIR/steps/vtr-min-setup.sh
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else
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source $SCRIPT_DIR/steps/vtr-full-setup.sh

.github/workflows/test.yml

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@@ -199,7 +199,7 @@ jobs:
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./.github/travis/setup.sh
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ODINII:
202-
name: 'ODIN-II Micro Tests'
202+
name: 'ODIN-II Basic Tests'
203203
runs-on: ubuntu-18.04
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steps:
205205

@@ -219,7 +219,7 @@ jobs:
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source .github/travis/common.sh
220220
./.github/travis/setup.sh
221221
./.github/travis/build.sh
222-
./run_reg_test.py odin_reg_micro -show_failures -j2
222+
./run_reg_test.py odin_reg_basic -show_failures -j2
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./.github/travis/setup.sh
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ODIN_II/SRC/ast_elaborate.cpp

Lines changed: 5 additions & 2 deletions
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@@ -1813,8 +1813,11 @@ ast_node_t* reduce_expressions(ast_node_t* node, sc_hierarchy* local_ref, long*
18131813

18141814
vtr::free(max_size);
18151815

1816-
/* cast to unsigned if necessary */
1817-
if (node_is_constant(node->children[1])) {
1816+
/*
1817+
* cast to unsigned if necessary
1818+
* Concatenate results are unsigned, regardless of the operands. IEEE.1364-2005 pp.65
1819+
*/
1820+
if (node->children[0]->type != CONCATENATE && node_is_constant(node->children[1])) {
18181821
char* id = NULL;
18191822
if (node->children[0]->type == IDENTIFIERS) {
18201823
id = node->children[0]->types.identifier;

README.developers.md

Lines changed: 4 additions & 4 deletions
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@@ -285,14 +285,14 @@ $ ./run_reg_test.py vtr_reg_basic vtr_reg_strong -j4
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Odin has its own set of tests to verify the correctness of its synthesis results:
287287

288-
* `odin_reg_micro`: ~2 minutes serial
289-
* `odin_reg_full`: ~6 minutes serial
288+
* `odin_reg_basic`: ~2 minutes serial
289+
* `odin_reg_strong`: ~6 minutes serial
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291291
These can be run with:
292292
```shell
293293
#From the VTR root directory
294-
$ ./run_reg_test.py odin_reg_micro
295-
$ ./run_reg_test.py odin_reg_full
294+
$ ./run_reg_test.py odin_reg_basic
295+
$ ./run_reg_test.py odin_reg_strong
296296
```
297297
and should be used when making changes to Odin.
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run_reg_test.py

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@@ -269,12 +269,12 @@ def run_odin_test(args, test_name):
269269
odin_reg_script[-1] += "task/arch_sweep"
270270
elif test_name == "odin_reg_operators":
271271
odin_reg_script[-1] += "task/operators"
272-
elif test_name == "odin_reg_large":
273-
odin_reg_script[-1] += "task/large"
274272
elif test_name == "odin_reg":
275273
odin_reg_script[-1] += "task/full"
276-
elif test_name == "odin_reg_micro":
274+
elif test_name == "odin_reg_basic":
277275
odin_reg_script[-1] += "suite/light_suite"
276+
elif test_name == "odin_reg_strong":
277+
odin_reg_script[-1] += "suite/heavy_suite"
278278
else:
279279
raise IOError("Test does not exist: {}".format(test_name))
280280

utils/fasm/test/test_fasm.cpp

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,22 @@ TEST_CASE("match_lut_init", "[fasm]") {
169169
CHECK(match_lut_init("16'b0000000011111111", "16'b0000111100001111"));
170170
}
171171

172-
std::string get_pin_feature (size_t inode) {
172+
/*
173+
The following function returns a string describing a block pin given an IPIN/
174+
OPIN rr node index. This is needed to correlate rr nodes with port names as
175+
defined in the architecture and used for checking if genfasm correctlty honors
176+
equivalent port pins rotation.
177+
178+
The output pin description format is:
179+
"PIN_<xlow>_<ylow>_<sub_tile_type>_<sub_tile_port>_<port_pin_index>"
180+
181+
Pin decriptions returned by this functions are injected as FASM features to the
182+
edges of a rr graph that are immediately connected with pins from "outside"
183+
(not to from/to a SOURCE or SINK). Then, after genfasm is run they are identified,
184+
and decoded to get all the pin information. This allows to get information
185+
which block pins are used from the "FASM perspective".
186+
*/
187+
static std::string get_pin_feature (size_t inode) {
173188
auto& device_ctx = g_vpr_ctx.device();
174189

175190
// Get tile physical tile and the pin number
@@ -178,7 +193,8 @@ std::string get_pin_feature (size_t inode) {
178193
auto physical_tile = device_ctx.grid[ilow][jlow].type;
179194
int pin_num = device_ctx.rr_nodes[inode].ptc_num();
180195

181-
// Get the sub tile (type, not instance)
196+
// Get the sub tile (type, not instance) and index of its pin that matches
197+
// the node index.
182198
const t_sub_tile* sub_tile_type = nullptr;
183199
int sub_tile_pin = -1;
184200

@@ -200,14 +216,13 @@ std::string get_pin_feature (size_t inode) {
200216
REQUIRE(sub_tile_type != nullptr);
201217
REQUIRE(sub_tile_pin != -1);
202218

203-
// Find the sub tile port and pin index
219+
// Find the sub tile port and pin index for the sub-tile type pin index.
204220
for (const auto& port : sub_tile_type->ports) {
205221
int pin_lo = port.absolute_first_pin_index;
206222
int pin_hi = pin_lo + port.num_pins;
207223

208224
if (sub_tile_pin >= pin_lo && sub_tile_pin < pin_hi) {
209225
int port_pin = sub_tile_pin - pin_lo;
210-
fprintf(stderr, " %zu %s %d\n", inode, port.name, port_pin);
211226
return vtr::string_fmt("PIN_%d_%d_%s_%s_%d", ilow, jlow, sub_tile_type->name, port.name, port_pin);
212227
}
213228
}
@@ -331,7 +346,6 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
331346
if (line.find(".names") != std::string::npos) {
332347
REQUIRE(lut_def.length() > 0);
333348
lut_defs.push_back(lut_def);
334-
//fprintf(stderr, "'%s'\n", lut_def.c_str());
335349
lut_def = "";
336350
continue;
337351
}
@@ -568,7 +582,6 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
568582
// Decompose the xbar feature - extract only the necessary information
569583
// such as block location and pin index.
570584
std::smatch m;
571-
fprintf(stderr, "%s\n", xbar_feature.c_str());
572585
auto res = std::regex_match(xbar_feature, m, std::regex(
573586
".*_X([0-9]+)Y([0-9]+)\\.IN([0-9])_XBAR_I([0-9]+)$"));
574587
REQUIRE(res == true);

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