@@ -385,6 +385,13 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) {
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}
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vpr_create_device (vpr_setup, arch);
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+ if (vpr_setup.PackerOpts .doPacking != STAGE_SKIP) {
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+ float target_device_utilization = vpr_setup.PackerOpts .target_device_utilization ;
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+ // Print the number of resources in netlist and number of resources available in architecture
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+ print_resource_usage (target_device_utilization);
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+ // Print the device utilization
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+ print_device_utilization (target_device_utilization);
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+ }
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// TODO: Placer still assumes that cluster net list is used - graphics can not work with flat routing yet
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vpr_init_graphics (vpr_setup, arch, false );
@@ -498,59 +505,6 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) {
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*/
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size_t num_grid_tiles = count_grid_tiles (device_ctx.grid );
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VTR_LOG (" FPGA sized to %zu x %zu: %zu grid tiles (%s)\n " , device_ctx.grid .width (), device_ctx.grid .height (), num_grid_tiles, device_ctx.grid .name ().c_str ());
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-
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- VTR_LOG (" \n " );
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- VTR_LOG (" Resource usage...\n " );
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- for (const auto & type : device_ctx.logical_block_types ) {
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- if (is_empty_type (&type)) continue ;
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-
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- VTR_LOG (" \t Netlist\n\t\t %d\t blocks of type: %s\n " ,
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- num_type_instances[&type], type.name .c_str ());
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-
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- VTR_LOG (" \t Architecture\n " );
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- for (const auto equivalent_tile : type.equivalent_tiles ) {
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- auto num_instances = 0 ;
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- // get the number of equivalent tile across all layers
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- num_instances = (int )device_ctx.grid .num_instances (equivalent_tile, -1 );
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-
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- VTR_LOG (" \t\t %d\t blocks of type: %s\n " ,
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- num_instances, equivalent_tile->name .c_str ());
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- }
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- }
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- VTR_LOG (" \n " );
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-
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- float device_utilization = calculate_device_utilization (device_ctx.grid , num_type_instances);
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- VTR_LOG (" Device Utilization: %.2f (target %.2f)\n " , device_utilization, target_device_utilization);
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- for (const auto & type : device_ctx.physical_tile_types ) {
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- if (is_empty_type (&type)) {
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- continue ;
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- }
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-
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- if (device_ctx.grid .num_instances (&type, -1 ) != 0 ) {
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- VTR_LOG (" \t Physical Tile %s:\n " , type.name .c_str ());
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-
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- auto equivalent_sites = get_equivalent_sites_set (&type);
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-
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- for (auto logical_block : equivalent_sites) {
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- float util = 0 .;
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- size_t num_inst = device_ctx.grid .num_instances (&type, -1 );
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- if (num_inst != 0 ) {
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- util = float (num_type_instances[logical_block]) / num_inst;
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- }
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- VTR_LOG (" \t Block Utilization: %.2f Logical Block: %s\n " , util, logical_block->name .c_str ());
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- }
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- }
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- }
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- VTR_LOG (" \n " );
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-
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- if (!device_ctx.grid .limiting_resources ().empty ()) {
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- std::vector<std::string> limiting_block_names;
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- for (auto blk_type : device_ctx.grid .limiting_resources ()) {
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- limiting_block_names.emplace_back (blk_type->name );
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- }
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- VTR_LOG (" FPGA size limited by block type(s): %s\n " , vtr::join (limiting_block_names, " " ).c_str ());
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- VTR_LOG (" \n " );
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- }
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}
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void vpr_setup_clock_networks (t_vpr_setup& vpr_setup, const t_arch& Arch) {
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