Merge pull request #3081 from AlexandreSinger/feature-include-cleanup

[Infra] Cleaned Up Includes in Non-External Libs

Author: AlexandreSinger

libs/libarchfpga/src/arch_check.cpp

@@ -1,5 +1,7 @@
 #include <set>
+#include <sstream>
 
+#include "arch_util.h"
 #include "logic_types.h"
 #include "vtr_log.h"
 #include "arch_error.h"

libs/libarchfpga/src/arch_check.h

@@ -1,5 +1,4 @@
-#ifndef ARCH_CHECK_H
-#define ARCH_CHECK_H
+#pragma once
 
 /**
  *  This file includes all the definitions of functions which purpose is to
@@ -8,12 +7,9 @@
  *  All new functions corresponding to the architecture checking should end up here.
  */
 
-#include "arch_types.h"
-#include "arch_util.h"
-
-#include "physical_types_util.h"
-
-#include "vtr_util.h"
+#include <stdint.h>
+#include "logic_types.h"
+#include "physical_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -76,5 +72,3 @@ void check_models(t_arch* arch);
 #ifdef __cplusplus
 }
 #endif
-
-#endif

libs/libarchfpga/src/arch_error.h

@@ -1,5 +1,4 @@
-#ifndef ARCH_ERROR_H
-#define ARCH_ERROR_H
+#pragma once
 
 #include "vtr_error.h"
 #include <cstdarg>
@@ -14,5 +13,3 @@ class ArchFpgaError : public vtr::VtrError {
     ArchFpgaError(std::string msg = "", std::string new_filename = "", size_t new_linenumber = -1)
         : vtr::VtrError(msg, new_filename, new_linenumber) {}
 };
-
-#endif

libs/libarchfpga/src/arch_types.h

@@ -1,17 +1,11 @@
+#pragma once
 /*
  * Data types describing the FPGA architecture.
  *
  * Date: February 19, 2009
  * Authors: Jason Luu and Kenneth Kent
  */
 
-#ifndef ARCH_TYPES_H
-#define ARCH_TYPES_H
-
-#include "logic_types.h"
-#include "physical_types.h"
-#include "cad_types.h"
-
 /* Input file parsing. */
 #define TOKENS " \t\n"
 
@@ -25,5 +19,3 @@ enum class e_arch_format {
     VTR,            ///<VTR-specific device XML format
     FPGAInterchange ///<FPGA Interchange device format
 };
-
-#endif

libs/libarchfpga/src/arch_util.h

@@ -1,7 +1,5 @@
-#ifndef ARCH_UTIL_H
-#define ARCH_UTIL_H
+#pragma once
 
-#include <regex>
 #include <unordered_set>
 #include "physical_types.h"
 
@@ -114,4 +112,3 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
                                  std::vector<t_logical_block_type>& LogicalBlockTypes);
 
 void setup_pin_classes(t_physical_tile_type* type);
-#endif

libs/libarchfpga/src/cad_types.h

@@ -1,10 +1,8 @@
+#pragma once
 /*
  * Data types used to give architectural hints for the CAD algorithm
  */
-#ifndef CAD_TYPES_H
-#define CAD_TYPES_H
 
-#include "logic_types.h"
 #include "physical_types.h"
 
 struct t_pack_pattern_connections;
@@ -128,5 +126,3 @@ struct t_cluster_placement_primitive {
     float base_cost;        /* cost independent of current status of packing */
     float incremental_cost; /* cost dependent on current status of packing */
 };
-
-#endif

libs/libarchfpga/src/clock_types.h

@@ -1,8 +1,6 @@
-#ifndef CLOCK_TYPES_H
-#define CLOCK_TYPES_H
+#pragma once
 
 #include <string>
-#include <vector>
 
 enum class e_clock_type {
     SPINE,
@@ -59,5 +57,3 @@ struct t_clock_connection_arch {
     std::string locationy;
     float fc;
 };
-
-#endif

libs/libarchfpga/src/device_grid.h

@@ -1,5 +1,4 @@
-#ifndef DEVICE_GRID
-#define DEVICE_GRID
+#pragma once
 
 #include <string>
 #include <vector>
@@ -149,5 +148,3 @@ class DeviceGrid {
 
     std::vector<t_logical_block_type_ptr> limiting_resources_;
 };
-
-#endif

libs/libarchfpga/src/echo_arch.h

@@ -1,11 +1,9 @@
-#ifndef ECHO_ARCH_H
-#define ECHO_ARCH_H
+#pragma once
 
-#include "arch_types.h"
+#include <vector>
+#include "physical_types.h"
 
 void EchoArch(const char* EchoFile,
               const std::vector<t_physical_tile_type>& PhysicalTileTypes,
               const std::vector<t_logical_block_type>& LogicalBlockTypes,
               const t_arch* arch);
-
-#endif

libs/libarchfpga/src/histogram.cpp

@@ -1,6 +1,5 @@
 #include <algorithm>
 #include <string>
-#include <sstream>
 #include <cmath>
 
 #include "vtr_log.h"

libs/libarchfpga/src/histogram.h

@@ -1,7 +1,7 @@
-#ifndef VPR_HISTOGRAM_H
-#define VPR_HISTOGRAM_H
+#pragma once
 
 #include <limits>
+#include <string>
 #include <vector>
 
 struct HistogramBucket {
@@ -22,5 +22,3 @@ void print_histogram(std::vector<HistogramBucket> histogram);
 float get_histogram_mode(std::vector<HistogramBucket> histogram);
 
 std::vector<std::string> format_histogram(std::vector<HistogramBucket> histogram, size_t width = 80);
-
-#endif

libs/libarchfpga/src/logic_types.h

@@ -1,3 +1,4 @@
+#pragma once
 /*
  * Data types describing the logic (technology-mapped) models that the architecture can implement.
  * Logic models include LUT (.names), flipflop (.latch), inpad, outpad, memory slice, etc.
@@ -10,9 +11,6 @@
  * Date: April, 2025
  */
 
-#ifndef LOGIC_TYPES_H
-#define LOGIC_TYPES_H
-
 #include "vtr_assert.h"
 #include "vtr_list.h"
 #include "vtr_memory.h"
@@ -275,5 +273,3 @@ class LogicalModels {
     /// @brief A lookup between the name of a logical model and its ID.
     std::unordered_map<std::string, LogicalModelId> model_name_to_logical_model_id_;
 };
-
-#endif

libs/libarchfpga/src/parse_switchblocks.h

@@ -1,9 +1,8 @@
-#ifndef PARSE_SWITCHBLOCKS_H
-#define PARSE_SWITCHBLOCKS_H
+#pragma once
 
-#include <vector>
+#include "physical_types.h"
 #include "pugixml.hpp"
-#include "pugixml_util.hpp"
+#include "pugixml_loc.hpp"
 #include "vtr_expr_eval.h"
 
 /**** Function Declarations ****/
@@ -18,5 +17,3 @@ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch);
 
 /* returns integer result according to the specified formula and data */
 int get_sb_formula_raw_result(vtr::FormulaParser& formula_parser, const char* formula, const vtr::t_formula_data& mydata);
-
-#endif /* PARSE_SWITCHBLOCKS_H */

libs/libarchfpga/src/physical_types.h

@@ -1,3 +1,4 @@
+#pragma once
 /*
  * Data types describing the physical components on the FPGA architecture.
  *
@@ -24,8 +25,6 @@
  * Authors: Jason Luu and Kenneth Kent
  */
 
-#pragma once
-
 #include <functional>
 #include <utility>
 #include <vector>
@@ -34,12 +33,9 @@
 #include <map>
 #include <unordered_map>
 #include <limits>
-#include <numeric>
-#include <set>
 #include <unordered_set>
 
 #include "vtr_ndmatrix.h"
-#include "vtr_hash.h"
 #include "vtr_bimap.h"
 #include "vtr_string_interning.h"
 

libs/libarchfpga/src/physical_types_util.cpp

@@ -1,10 +1,7 @@
-#include <set>
+#include <numeric>
 #include "vtr_assert.h"
-#include "vtr_memory.h"
 #include "vtr_util.h"
 
-#include "arch_types.h"
-#include "arch_util.h"
 #include "arch_error.h"
 
 #include "physical_types_util.h"

libs/libarchfpga/src/physical_types_util.h

@@ -1,8 +1,4 @@
-
 #pragma once
-
-#include "physical_types.h"
-
 /********************************************************************
  *                                                                  *
  *  Physical types utility functions                                *
@@ -114,6 +110,8 @@
  * and CLK_2 (physical pin) from the BUFG (logical block) and CLOCK TILE (physical tile).
  */
 
+#include "physical_types.h"
+
 ///@brief Returns true if the absolute physical pin index is an output of the given physical tile type
 bool is_opin(int ipin, t_physical_tile_type_ptr type);
 

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -1,10 +1,15 @@
 
-
 #include "read_fpga_interchange_arch.h"
-#include "logic_types.h"
 
 #ifdef VTR_ENABLE_CAPNPROTO
 
+#include <numeric>
+#include "LogicalNetlist.capnp.h"
+#include "logic_types.h"
+#include "DeviceResources.capnp.h"
+#include "LogicalNetlist.capnp.h"
+#include "capnp/serialize.h"
+
 #include <algorithm>
 #include <kj/std/iostream.h>
 #include <limits>
@@ -26,6 +31,15 @@
 #include "arch_error.h"
 #include "arch_util.h"
 
+#else // VTR_ENABLE_CAPNPROTO
+
+#include <vector>
+#include "physical_types.h"
+#include "vtr_error.h"
+
+#endif // VTR_ENABLE_CAPNPROTO
+
+#ifdef VTR_ENABLE_CAPNPROTO
 /*
  * FPGA Interchange Device frontend
  *

libs/libarchfpga/src/read_fpga_interchange_arch.h

@@ -1,18 +1,7 @@
-#ifndef READ_FPGAINTERCHANGE_ARCH_FILE_H
-#define READ_FPGAINTERCHANGE_ARCH_FILE_H
+#pragma once
 
-#include "arch_types.h"
-
-#ifdef VTR_ENABLE_CAPNPROTO
-
-#include "DeviceResources.capnp.h"
-#include "LogicalNetlist.capnp.h"
-#include "capnp/serialize.h"
-#include "capnp/serialize-packed.h"
-#include <fcntl.h>
-#include <unistd.h>
-
-#endif // VTR_ENABLE_CAPNPROTO
+#include <vector>
+#include "physical_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -34,5 +23,3 @@ void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile,
 #ifdef __cplusplus
 }
 #endif
-
-#endif

libs/libarchfpga/src/read_xml_arch_file.h

@@ -1,7 +1,7 @@
-#ifndef READ_XML_ARCH_FILE_H
-#define READ_XML_ARCH_FILE_H
+#pragma once
 
-#include "arch_types.h"
+#include <vector>
+#include "physical_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -21,5 +21,3 @@ void XmlReadArch(const char* ArchFile,
 #ifdef __cplusplus
 }
 #endif
-
-#endif

libs/libarchfpga/src/read_xml_arch_file_noc_tag.h

@@ -1,6 +1,4 @@
-
-#ifndef VTR_READ_XML_ARCH_FILE_NOC_TAG_H
-#define VTR_READ_XML_ARCH_FILE_NOC_TAG_H
+#pragma once
 
 #include "pugixml.hpp"
 #include "pugixml_loc.hpp"
@@ -37,5 +35,3 @@ struct t_mesh_region {
     /// The number of NoC routers in each row or column.
     int mesh_size;
 };
-
-#endif //VTR_READ_XML_ARCH_FILE_NOC_TAG_H

libs/libarchfpga/src/read_xml_util.h

@@ -1,5 +1,4 @@
-#ifndef READ_XML_UTIL_H
-#define READ_XML_UTIL_H
+#pragma once
 
 #include "pugixml.hpp"
 #include "pugixml_loc.hpp"
@@ -24,5 +23,3 @@ void bad_attribute_value(const pugi::xml_attribute attr,
 
 InstPort make_inst_port(std::string str, pugi::xml_node node, const pugiutil::loc_data& loc_data);
 InstPort make_inst_port(pugi::xml_attribute attr, pugi::xml_node node, const pugiutil::loc_data& loc_data);
-
-#endif

libs/libarchfpga/src/write_models_bb.h

@@ -1,10 +1,7 @@
-#ifndef WRITE_MODELS_BB_H
-#define WRITE_MODELS_BB_H
+#pragma once
 
-#include "arch_types.h"
+#include "physical_types.h"
 
 void WriteModels_bb(const char* ArchFile,
                     const char* VEchoFile,
                     const t_arch* arch);
-
-#endif