Merge branch 'librrgraph_vpr' of github.com:oscarcheng105/vtr-verilog-to-routing into librrgraph_vpr

Author: oscarcheng105

.github/workflows/test.yml

@@ -331,14 +331,14 @@ jobs:
       fail-fast: false
       matrix:
         include:
-        - { name: 'GCC 7 (Ubuntu Bionic - 18.04)',    eval: 'CC=gcc-7 && CXX=g++-7',           build: ''               }
-        - { name: 'GCC 8 (Debian Buster)',            eval: 'CC=gcc-8 && CXX=g++-8',           build: ''               }
-        - { name: 'GCC 9 (Ubuntu Focal - 20.04)',     eval: 'CC=gcc-9 && CXX=g++-9',           build: ''               }
-        - { name: 'GCC 10 (Ubuntu Hirsute - 21.04)',  eval: 'CC=gcc-10 && CXX=g++-10',         build: ''               }
-        - { name: 'GCC 11 (Latest)',                  eval: 'CC=gcc-11 && CXX=g++-11',         build: ''               }
-        - { name: 'Clang 6 (Ubuntu Bionic - 18.04)',  eval: 'CC=clang-6.0 && CXX=clang++-6.0', build: ''               }
-        - { name: 'Clang 7 (Debian Buster)',          eval: 'CC=clang-7 && CXX=clang++-7',     build: ''               }
-        - { name: 'Clang 10 (Ubuntu Focal - 20.04)',  eval: 'CC=clang-10 && CXX=clang++-10',   build: ''               }
+        - { name: 'GCC 7 (Ubuntu Bionic - 18.04)',    eval: 'CC=gcc-7 && CXX=g++-7',           }
+        - { name: 'GCC 8 (Debian Buster)',            eval: 'CC=gcc-8 && CXX=g++-8',           }
+        - { name: 'GCC 9 (Ubuntu Focal - 20.04)',     eval: 'CC=gcc-9 && CXX=g++-9',           }
+        - { name: 'GCC 10 (Ubuntu Hirsute - 21.04)',  eval: 'CC=gcc-10 && CXX=g++-10',         }
+        - { name: 'GCC 11 (Latest)',                  eval: 'CC=gcc-11 && CXX=g++-11',         }
+        - { name: 'Clang 6 (Ubuntu Bionic - 18.04)',  eval: 'CC=clang-6.0 && CXX=clang++-6.0', }
+        - { name: 'Clang 7 (Debian Buster)',          eval: 'CC=clang-7 && CXX=clang++-7',     }
+        - { name: 'Clang 10 (Ubuntu Focal - 20.04)',  eval: 'CC=clang-10 && CXX=clang++-10',   }
     name: 'B: ${{ matrix.name }}'
     steps:
 
@@ -354,7 +354,7 @@ jobs:
       env:
         CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on"
         MATRIX_EVAL: ${{ matrix.eval }}
-        BUILD_TYPE: ${{ matrix.build }}
+        BUILD_TYPE: release
       run: |
         export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
         ./.github/scripts/build.sh

ODIN_II/main.cpp

@@ -2,6 +2,7 @@
 #include "odin_types.h"
 #include "vtr_time.h"
 #include "vtr_version.h"
+#include <sys/resource.h>
 
 int main(int argc, char** argv) {
     vtr::ScopedFinishTimer t("Odin II");
@@ -27,6 +28,19 @@ int main(int argc, char** argv) {
         "\n",
         vtr::VERSION, vtr::VCS_REVISION, vtr::BUILD_TIMESTAMP, vtr::COMPILER, vtr::BUILD_INFO);
 
+/**
+ * set stack size to >= 128 MB in linux operating systems to avoid
+ * stack overflow in recursive routine calls for big benchmarks 
+ */
+#ifdef __linux__
+    struct rlimit rl;
+    const rlim_t new_stack_size = 128L * 1024L * 1024L;
+    if (getrlimit(RLIMIT_STACK, &rl) == 0 && rl.rlim_cur < new_stack_size) {
+        rl.rlim_cur = new_stack_size;
+        setrlimit(RLIMIT_STACK, &rl);
+    }
+#endif
+
     netlist_t* odin_netlist = start_odin_ii(argc, argv);
     terminate_odin_ii(odin_netlist);
     return 0;

libs/libarchfpga/src/arch_util.cpp

@@ -298,7 +298,7 @@ static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_desc
         if (type.pb_type) {
             if (type.pb_graph_head) {
                 free_pb_graph(type.pb_graph_head);
-                vtr::free(type.pb_graph_head);
+                delete type.pb_graph_head;
             }
         }
     }
@@ -316,78 +316,46 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
     /* Free ports for pb graph node */
     for (i = 0; i < pb_graph_node->num_input_ports; i++) {
         for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
-            if (pb_graph_node->input_pins[i][j].pin_timing)
-                vtr::free(pb_graph_node->input_pins[i][j].pin_timing);
-            if (pb_graph_node->input_pins[i][j].pin_timing_del_max)
-                vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_max);
-            if (pb_graph_node->input_pins[i][j].pin_timing_del_min)
-                vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_min);
-            if (pb_graph_node->input_pins[i][j].input_edges)
-                vtr::free(pb_graph_node->input_pins[i][j].input_edges);
-            if (pb_graph_node->input_pins[i][j].output_edges)
-                vtr::free(pb_graph_node->input_pins[i][j].output_edges);
             if (pb_graph_node->input_pins[i][j].parent_pin_class)
-                vtr::free(pb_graph_node->input_pins[i][j].parent_pin_class);
+                delete[] pb_graph_node->input_pins[i][j].parent_pin_class;
         }
         delete[] pb_graph_node->input_pins[i];
     }
     for (i = 0; i < pb_graph_node->num_output_ports; i++) {
         for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
-            if (pb_graph_node->output_pins[i][j].pin_timing)
-                vtr::free(pb_graph_node->output_pins[i][j].pin_timing);
-            if (pb_graph_node->output_pins[i][j].pin_timing_del_max)
-                vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_max);
-            if (pb_graph_node->output_pins[i][j].pin_timing_del_min)
-                vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_min);
-            if (pb_graph_node->output_pins[i][j].input_edges)
-                vtr::free(pb_graph_node->output_pins[i][j].input_edges);
-            if (pb_graph_node->output_pins[i][j].output_edges)
-                vtr::free(pb_graph_node->output_pins[i][j].output_edges);
             if (pb_graph_node->output_pins[i][j].parent_pin_class)
-                vtr::free(pb_graph_node->output_pins[i][j].parent_pin_class);
+                delete[] pb_graph_node->output_pins[i][j].parent_pin_class;
 
             if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) {
                 for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
-                    if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) {
-                        vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]);
-                    }
+                    delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k];
                 }
-                vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs);
+                delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs;
             }
 
             if (pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins)
-                vtr::free(pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins);
+                delete[] pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins;
         }
         delete[] pb_graph_node->output_pins[i];
     }
     for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
         for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
-            if (pb_graph_node->clock_pins[i][j].pin_timing)
-                vtr::free(pb_graph_node->clock_pins[i][j].pin_timing);
-            if (pb_graph_node->clock_pins[i][j].pin_timing_del_max)
-                vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_max);
-            if (pb_graph_node->clock_pins[i][j].pin_timing_del_min)
-                vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_min);
-            if (pb_graph_node->clock_pins[i][j].input_edges)
-                vtr::free(pb_graph_node->clock_pins[i][j].input_edges);
-            if (pb_graph_node->clock_pins[i][j].output_edges)
-                vtr::free(pb_graph_node->clock_pins[i][j].output_edges);
             if (pb_graph_node->clock_pins[i][j].parent_pin_class)
-                vtr::free(pb_graph_node->clock_pins[i][j].parent_pin_class);
+                delete[] pb_graph_node->clock_pins[i][j].parent_pin_class;
         }
         delete[] pb_graph_node->clock_pins[i];
     }
 
-    vtr::free(pb_graph_node->input_pins);
-    vtr::free(pb_graph_node->output_pins);
-    vtr::free(pb_graph_node->clock_pins);
+    delete[] pb_graph_node->input_pins;
+    delete[] pb_graph_node->output_pins;
+    delete[] pb_graph_node->clock_pins;
 
-    vtr::free(pb_graph_node->num_input_pins);
-    vtr::free(pb_graph_node->num_output_pins);
-    vtr::free(pb_graph_node->num_clock_pins);
+    delete[] pb_graph_node->num_input_pins;
+    delete[] pb_graph_node->num_output_pins;
+    delete[] pb_graph_node->num_clock_pins;
 
-    vtr::free(pb_graph_node->input_pin_class_size);
-    vtr::free(pb_graph_node->output_pin_class_size);
+    delete[] pb_graph_node->input_pin_class_size;
+    delete[] pb_graph_node->output_pin_class_size;
 
     if (pb_graph_node->interconnect_pins) {
         for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) {
@@ -403,19 +371,19 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
 
                 t_interconnect_power* interconn_power = interconn->interconnect_power;
                 for (int iport = 0; iport < interconn_power->num_input_ports; ++iport) {
-                    vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins[iport]);
+                    delete[] pb_graph_node->interconnect_pins[i][j].input_pins[iport];
                 }
                 for (int iport = 0; iport < interconn_power->num_output_ports; ++iport) {
-                    vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins[iport]);
+                    delete[] pb_graph_node->interconnect_pins[i][j].output_pins[iport];
                 }
-                vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins);
-                vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins);
+                delete[] pb_graph_node->interconnect_pins[i][j].input_pins;
+                delete[] pb_graph_node->interconnect_pins[i][j].output_pins;
             }
-            vtr::free(pb_graph_node->interconnect_pins[i]);
+            delete[] pb_graph_node->interconnect_pins[i];
         }
     }
-    vtr::free(pb_graph_node->interconnect_pins);
-    vtr::free(pb_graph_node->pb_node_power);
+    delete[] pb_graph_node->interconnect_pins;
+    delete pb_graph_node->pb_node_power;
 
     for (i = 0; i < pb_type->num_modes; i++) {
         for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {

libs/libarchfpga/src/physical_types.h

@@ -1235,9 +1235,9 @@ class t_pb_graph_pin {
   public:
     t_port* port = nullptr;
     int pin_number = 0;
-    t_pb_graph_edge** input_edges = nullptr; /* [0..num_input_edges] */
+    std::vector<t_pb_graph_edge*> input_edges; /* [0..num_input_edges] */
     int num_input_edges = 0;
-    t_pb_graph_edge** output_edges = nullptr; /* [0..num_output_edges] */
+    std::vector<t_pb_graph_edge*> output_edges; /* [0..num_output_edges] */
     int num_output_edges = 0;
 
     t_pb_graph_node* parent_node = nullptr;
@@ -1256,9 +1256,9 @@ class t_pb_graph_pin {
 
     /* combinational timing information */
     int num_pin_timing = 0;                   /* Number of ipin to opin timing edges*/
-    t_pb_graph_pin** pin_timing = nullptr;    /* timing edge sink pins  [0..num_pin_timing-1]*/
-    float* pin_timing_del_max = nullptr;      /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
-    float* pin_timing_del_min = nullptr;      /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
+    std::vector<t_pb_graph_pin*> pin_timing;  /* timing edge sink pins  [0..num_pin_timing-1]*/
+    std::vector<float> pin_timing_del_max;    /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
+    std::vector<float> pin_timing_del_min;    /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
     int num_pin_timing_del_max_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_max_annotated-1]
     int num_pin_timing_del_min_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_min_annotated-1]
 
@@ -1333,7 +1333,7 @@ class t_pb_graph_edge {
 
     /* pack pattern info */
     int num_pack_patterns;
-    const char** pack_pattern_names;
+    std::vector<const char*> pack_pattern_names;
     int* pack_pattern_indices;
     bool infer_pattern;
 

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -4672,7 +4672,7 @@ static void processTopology(pugi::xml_node topology_tag, const pugiutil::loc_dat
     /**
      * Stores router information that includes the number of connections a router has within a given topology and also the number of times a router was declared in the arch file using the <router> tag.
      * In the datastructure below, the router id is the key and the stored data is a pair, where the first element describes the number of router declarations and the second element describes the number of router connections.
-     * This is used only for erro checking.
+     * This is used only for error checking.
      */
     std::map<int, std::pair<int, int>> routers_in_arch_info;
 

libs/libvtrutil/src/vtr_memory.cpp

@@ -6,6 +6,7 @@
 #include "vtr_memory.h"
 #include "vtr_error.h"
 #include "vtr_util.h"
+#include "vtr_log.h"
 
 #ifndef __GLIBC__
 #    include <stdlib.h>

vpr/src/base/SetupVPR.cpp

@@ -665,6 +665,7 @@ static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t
 static void SetupNocOpts(const t_options& Options, t_noc_opts* NocOpts) {
     // assign the noc specific options from the command line
     NocOpts->noc = Options.noc;
+    NocOpts->noc_flows_file = Options.noc_flows_file;
 
     return;
 }

vpr/src/base/ShowSetup.cpp

@@ -20,6 +20,7 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts,
                            const t_annealing_sched& AnnealSched);
 static void ShowRouterOpts(const t_router_opts& RouterOpts);
 static void ShowAnalysisOpts(const t_analysis_opts& AnalysisOpts);
+static void ShowNocOpts(const t_noc_opts& NocOpts);
 
 static void ShowAnnealSched(const t_annealing_sched& AnnealSched);
 
@@ -61,6 +62,9 @@ void ShowSetup(const t_vpr_setup& vpr_setup) {
     if (vpr_setup.AnalysisOpts.doAnalysis) {
         ShowAnalysisOpts(vpr_setup.AnalysisOpts);
     }
+    if (vpr_setup.NocOpts.noc) {
+        ShowNocOpts(vpr_setup.NocOpts);
+    }
 }
 
 void ClusteredNetlistStats::writeHuman(std::ostream& output) const {
@@ -764,3 +768,10 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) {
     VTR_LOG("\n");
     VTR_LOG("\n");
 }
+
+static void ShowNocOpts(const t_noc_opts& NocOpts) {
+    VTR_LOG("NocOpts.noc_flows_file: %s\n", NocOpts.noc_flows_file.c_str());
+    VTR_LOG("\n");
+
+    // add future options here (routing algorithm etc...)
+}

vpr/src/base/clustered_netlist.cpp

@@ -306,3 +306,17 @@ bool ClusteredNetlist::validate_net_sizes_impl(size_t num_nets) const {
     }
     return true;
 }
+
+ClusterBlockId ClusteredNetlist::find_block_by_name_fragment(const std::string& name_pattern, const std::vector<ClusterBlockId>& cluster_block_candidates) const {
+    ClusterBlockId blk_id = ClusterBlockId::INVALID();
+    std::regex name_to_match(name_pattern);
+
+    for (auto compatible_block_id = cluster_block_candidates.begin(); compatible_block_id != cluster_block_candidates.end(); compatible_block_id++) {
+        if (std::regex_match(Netlist::block_name(*compatible_block_id), name_to_match)) {
+            blk_id = *compatible_block_id;
+            break;
+        }
+    }
+
+    return blk_id;
+}

vpr/src/base/clustered_netlist.h

@@ -228,6 +228,77 @@ class ClusteredNetlist : public Netlist<ClusterBlockId, ClusterPortId, ClusterPi
     ///@brief Sets the flag in net_is_global_ = state
     void set_net_is_global(ClusterNetId net_id, bool state);
 
+    /**
+     * @brief Given a name of a block and vector of possible cluster blocks
+     *        that are candidates to match the block name, go through 
+     *        the vector of cluster blocks and return the id of the block
+     *        where the block name matches the provided name.
+     * 
+     *        Given a string pattern representing a block name and a vector of
+     *        poissble cluster blocks that are candidates to match to the block
+     *        name pattern, go through the vector of cluster blocks and return 
+     *        the id of the block where the block name matches to the provided
+     *        input pattern.
+     * 
+     */
+
+    /**
+     * @brief The intented use is to find the block id of a 
+     *        hard block without knowing its name in the netlist. Instead
+     *        a pattern can be created that we know the block's name will
+     *        match to. Generally, we expect the pattern to be constructed
+     *        using the block's module name in the HDL design, since we can
+     *        expect the netlist name of the block to include the module
+     *        name within it.
+     * 
+     *        For example, suppose a RAM block was named in the netlist as
+     *        "top|alu|test_ram|out". The user instantiated the ram module
+     *        in the HDL design as "test_ram". So instead of going through 
+     *        the netlist and finding the ram block's full name, this
+     *        function can be used by just providing the string pattern as
+     *        ".*test_ram.*". We know that the module name should be somewhere
+     *        within the string, so the pattern we provide says that the netlist
+     *        name of the block contains arbritary characters then the module
+     *        name and then some other arbritary characters after.
+     *        This pattern will then be used to match to the block in the
+     *        netlist. The matched cluster block id is returned, and if no
+     *        block matched to the input string then an invalid block id
+     *        is returned.
+     * 
+     *        The function 
+     *        here additionally requires a vector of possible cluster blocks
+     *        that can match to the input pattern. This vector can be the
+     *        entire netlist or a subset. For example, if the intended use 
+     *        is to find hard blocks, it is quite inefficient
+     *        to go through all the blocks to find a matching one. Instead, a
+     *        a filtered vector can be passed that is a subset of the entire 
+     *        netlist and can only contain blocks of a certain logical block 
+     *        type (blocks that can be placed on a specific hard block).
+     *        The idea here is that the filtered vector should be
+     *        considereably smaller that a vector of every block in the netlist
+     *        and this should help improve run time.
+     * 
+     *        This function runs in linear time (O(N)) as it goes over the
+     *        vector of 'cluster_block_candidates'. 'cluster_block_candidates'
+     *        could be the whole netlist or a subset as explained above.
+     *        Additionally, if there are multiple
+     *        blocks that match to the provided input pattern, then the
+     *        first block found is returned.
+     * 
+     * 
+     * @param name_pattern A regex string pattern that can be used to match to  
+     *             a clustered block name within the netlist.
+     * @param cluster_block_candidates A vector of clustered block ids that
+     *                                 represent a subset of the clustered
+     *                                 netlist. The blocks in this vector
+     *                                 will be used to compare and match
+     *                                 to the input string pattern. 
+     * @return A cluster block id representing a unique cluster block that 
+     *         matched to the input string pattern.
+     *         
+     */
+    ClusterBlockId find_block_by_name_fragment(const std::string& name_pattern, const std::vector<ClusterBlockId>& cluster_block_candidates) const;
+
   private: //Private Members
     /*
      * Netlist compression/optimization

vpr/src/base/echo_files.cpp

@@ -132,6 +132,7 @@ void alloc_and_load_echo_file_info() {
 
     //NoC
     setEchoFileName(E_ECHO_NOC_MODEL, "noc_model.echo");
+    setEchoFileName(E_ECHO_NOC_TRAFFIC_FLOWS, "noc_traffic_flows.echo");
 }
 
 void free_echo_file_info() {

vpr/src/base/echo_files.h

@@ -65,6 +65,7 @@ enum e_echo_files {
 
     //NoC
     E_ECHO_NOC_MODEL,
+    E_ECHO_NOC_TRAFFIC_FLOWS,
 
     E_ECHO_END_TOKEN
 };