Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into skip_anneal

Author: amin1377

doc/src/vpr/placement_constraints.rst

@@ -18,7 +18,7 @@ A Placement Constraints File Example
 		<partition_list>
 			<partition name="Part0">
 					<add_atom name_pattern="li354"/>
-					<add_atom name_pattern="alu*"/> <!-- Regular expressions can be used to provide name patterns of the primitives to be added -->
+					<add_atom name_pattern="alu.*"/> <!-- Regular expressions can be used to provide name patterns of the primitives to be added -->
 					<add_atom name_pattern="n877"/>
 					<add_region x_low="3" y_low="1" x_high="7" y_high="2"/> <!-- Two rectangular regions are specified, together describing an L-shaped region -->
 					<add_region x_low="7" y_low="3" x_high="7" y_high="6"/>
@@ -78,7 +78,10 @@ An ``<add_atom>`` tag is used to add an atom that must be constrained to the par
 :req_param name_pattern:
    The name of the atom.
 
-The ``name_pattern`` can be the exact name of the atom from the input atom netlist that was passed to VPR. It can also be a regular expression, in which case VPR will add all atoms from the netlist which have a portion of their name matching the regular expression to the partition. For example, if a module contains primitives named in the pattern of "alu[0]", "alu[1]", and "alu[2]", the regular expression "alu*" would add all of the primitives from that module.
+The ``name_pattern`` can either be the exact name of an atom from the input atom netlist passed to VPR, or a regular expression pattern matching one or more atom names. VPR first searches the netlist for an exact match. If no exact match is found, it then assumes that the given name is a regex pattern and searches for atoms whose names match the pattern.
+
+For example, to add all atoms ``alu[0]``, ``alu[1]``, and ``alu[2]`` to the partition ``Part0``, the user can use ``alu.*`` as the ``name_pattern`` in the ``<add_atom>`` tag.
+
 
 Region
 ^^^^^^
@@ -124,12 +127,3 @@ It is strongly recommended that different partitions do not overlap. The packing
 blocks and the number of physical blocks in a region to decide pack atoms inside a partition more aggressively when
 there are not enough resources in a partition. Overlapping partitions causes some physical blocks to be counted in more
 than one partition.
-
-
-
-
-
-
-
-
-

libs/libarchfpga/src/echo_arch.cpp

@@ -297,7 +297,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
                 int num_layers = (int)layout.layers.size();
                 if (num_layers > 1) {
                     fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
-                            arch->switches[seg.arch_opin_between_dice_switch].name.c_str());
+                            arch->switches[seg.arch_inter_die_switch].name.c_str());
                 }
             }
         } else { //Should be bidir

libs/libarchfpga/src/physical_types.h

@@ -1599,88 +1599,138 @@ enum e_Fc_type {
     FRACTIONAL
 };
 
-/* Lists all the important information about a certain segment type.  Only   *
- * used if the route_type is DETAILED.  [0 .. det_routing_arch.num_segment]  *
- * name: the name of this segment                                            *
- * frequency:  ratio of tracks which are of this segment type.               *
- * length:     Length (in clbs) of the segment.                              *
- * arch_wire_switch: Index of the switch type that connects other wires      *
- *                   *to* this segment. Note that this index is in relation  *
- *                   to the switches from the architecture file, not the     *
- *                   expanded list of switches that is built at the end of   *
- *                   build_rr_graph.                                         *
- * arch_opin_switch: Index of the switch type that connects output pins      *
- *                   (OPINs) *to* this segment. Note that this index is in   *
- *                   relation to the switches from the architecture file,    *
- *                   not the expanded list of switches that is built         *
- *                   at the end of build_rr_graph                            *
- * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for   *
- *                   decremental tracks if it is specified in the            *
- *                   architecture file. If -1, this value was not set in     *
- *                   the architecture file and arch_wire_switch should be    *
- *                   used for "DEC_DIR" wire segments.                       *
- * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for   *
- *                   decremental tracks if it is specified in the            *
- *                   architecture file. If -1, this value was not set in     * 
- *                   the architecture file and arch_opin_switch should be    *
- *                   used for "DEC_DIR" wire segments.                       * 
- * @param arch_opin_between_dice_switch: Index of the switch type that       *
- *                   connects output pins (OPINs) *to* this segment from     *
- *                   *another die (layer)*. Note that this index is in       *
- *                   relation to the switches from the architecture file,    *
- *                   not the expanded list of switches that is built at      *
- *                   the end of build_rr_graph                               *
- *                                                                           *
- * frac_cb:  The fraction of logic blocks along its length to which this     *
- *           segment can connect.  (i.e. internal population).               *
- * frac_sb:  The fraction of the length + 1 switch blocks along the segment  *
- *           to which the segment can connect.  Segments that aren't long    *
- *           lines must connect to at least two switch boxes.                *
- * parallel_axis:   Defines what axis the segment is parallel to. See        *
- *                  e_parallel_axis comments for more details on the values. *
- * Cmetal: Capacitance of a routing track, per unit logic block length.      *
- * Rmetal: Resistance of a routing track, per unit logic block length.       *
- * (UDSD by AY) drivers: How do signals driving a routing track connect to   *
- *                       the track?                                          *
- * seg_index: The index of the segment as stored in the appropriate Segs list*
- *            Upon loading the architecture, we use this field to keep track *
- *            the segment's index in the unified segment_inf vector. This is *
- *            useful when building the rr_graph for different Y & X channels *
- *            in terms of track distribution and segment type.               *
- * res_type: Determines the routing network to which the segment belongs.    *
- *           Possible values are:                                            *
- *              - GENERAL: The segment is part of the general routing        *
- *                         resources.                                        *
- *              - GCLK: The segment is part of the global routing network.   *
- *           For backward compatibility, this attribute is optional. If not  *
- *           specified, the resource type for the segment is considered to   *
- *           be GENERAL.                                                     *
- * meta: Table storing extra arbitrary metadata attributes.                  */
+/**
+ * @brief Lists all the important information about a certain segment type.  Only
+ * used if the route_type is DETAILED.  [0 .. det_routing_arch.num_segment]
+ */
 struct t_segment_inf {
+    /**
+     *  @brief The name of the segment type 
+     */
     std::string name;
+
+    /**
+     *  @brief ratio of tracks which are of this segment type. 
+     */
     int frequency;
+
+    /**
+     *  @brief Length (in clbs) of the segment. 
+     */
     int length;
+
+    /**
+     *  @brief Index of the switch type that connects other wires to this segment. 
+     * Note that this index is in relation to the switches from the architecture file, 
+     * not the expanded list of switches that is built at the end of build_rr_graph. 
+     */
     short arch_wire_switch;
+
+    /**
+     *  @brief Index of the switch type that connects output pins to this segment. 
+     * Note that this index is in relation to the switches from the architecture file, 
+     * not the expanded list of switches that is built at the end of build_rr_graph. 
+     */
     short arch_opin_switch;
+
+    /**
+     *  @brief Same as arch_wire_switch but used only for decremental tracks if it is 
+     * specified in the architecture file. If -1, this value was not set in the 
+     * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. 
+     */
     short arch_wire_switch_dec = -1;
+
+    /**
+     *  @brief Same as arch_opin_switch but used only for decremental tracks if 
+     * it is specified in the architecture file. If -1, this value was not set in 
+     * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. 
+     */
     short arch_opin_switch_dec = -1;
-    short arch_opin_between_dice_switch = -1;
+
+    /**
+     *  @brief Index of the switch type that connects output pins (OPINs) to this 
+     * segment from another die (layer). Note that this index is in relation to 
+     * the switches from the architecture file, not the expanded list of switches 
+     * that is built at the end of build_rr_graph. 
+     */
+    short arch_inter_die_switch = -1;
+
+    /**
+     *  @brief The fraction of logic blocks along its length to which this segment can connect. 
+     * (i.e. internal population). 
+     */
     float frac_cb;
+
+    /**
+     *  @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. 
+     * Segments that aren't long lines must connect to at least two switch boxes. 
+     */
     float frac_sb;
+
     bool longline;
+
+    /**
+     *  @brief The resistance of a routing track, per unit logic block length. */
     float Rmetal;
+
+    /**
+     *  @brief The capacitance of a routing track, per unit logic block length. */
     float Cmetal;
+
     enum e_directionality directionality;
+
+    /**
+     *  @brief Defines what axis the segment is parallel to. See e_parallel_axis 
+     * comments for more details on the values. 
+     */
     enum e_parallel_axis parallel_axis;
+
+    /**
+     *  @brief A vector of booleans indicating whether the segment can connect to a logic block. 
+     */
     std::vector<bool> cb;
+
+    /**
+     *  @brief A vector of booleans indicating whether the segment can connect to a switch block. 
+     */
     std::vector<bool> sb;
+
+    /**
+     *  @brief The index of the segment as stored in the appropriate Segs list.
+     * Upon loading the architecture, we use this field to keep track of the 
+     * segment's index in the unified segment_inf vector. This is useful when 
+     * building the rr_graph for different Y & X channels in terms of track 
+     * distribution and segment type. 
+     */
     int seg_index;
+
+    /**
+     *  @brief Determines the routing network to which the segment belongs.
+     *  Possible values are:
+     *   - GENERAL: The segment is part of the general routing resources.
+     *   - GCLK: The segment is part of the global routing network.
+     * For backward compatibility, this attribute is optional. If not specified, 
+     * the resource type for the segment is considered to be GENERAL.
+     */
     enum SegResType res_type = SegResType::GENERAL;
-    //float Cmetal_per_m; /* Wire capacitance (per meter) */
 };
 
 inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) {
-    return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.arch_opin_between_dice_switch == b.arch_opin_between_dice_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
+    return a.name == b.name
+           && a.frequency == b.frequency
+           && a.length == b.length
+           && a.arch_wire_switch == b.arch_wire_switch
+           && a.arch_opin_switch == b.arch_opin_switch
+           && a.arch_inter_die_switch == b.arch_inter_die_switch
+           && a.frac_cb == b.frac_cb
+           && a.frac_sb == b.frac_sb
+           && a.longline == b.longline
+           && a.Rmetal == b.Rmetal
+           && a.Cmetal == b.Cmetal
+           && a.directionality == b.directionality
+           && a.parallel_axis == b.parallel_axis
+           && a.cb == b.cb
+           && a.sb == b.sb;
 }
 
 /*provide hashing for t_segment_inf to enable the use of many std containers.

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -3793,7 +3793,7 @@ static std::vector<t_segment_inf> ProcessSegments(pugi::xml_node Parent,
                 archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
                                "'%s' is not a valid mux name.\n", tmp);
             }
-            Segs[i].arch_opin_between_dice_switch = switch_idx;
+            Segs[i].arch_inter_die_switch = switch_idx;
         }
 
         /* Get the wire and opin switches, or mux switch if unidir */