[Yosys] Cleaned Up Some Small Issues

The changes made to Yosys added a few random lines which I removed.

Added some comments explaining why certain tests were turned off.

Upgraded libcatch to match master since the PR would have downgraded
master by mistake.

Author: AlexandreSinger

.github/workflows/nightly_test.yml

@@ -49,7 +49,7 @@ jobs:
       matrix:
         include:
           - {test: "vtr_reg_nightly_test1",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}          
+          - {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
           - {test: "vtr_reg_nightly_test2",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
           - {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
           - {test: "vtr_reg_nightly_test3",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
@@ -62,7 +62,7 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          #- {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} Test turned off -> F4PGA conflicts with Yosys (version 42)
+          # - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
           - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=OFF",                                     extra_pkgs: ""}
 

libs/EXTERNAL/libcatch2

@@ -109,7 +109,6 @@ class Point {
     T y_;
 };
 
-
 /**
  * @brief A 2D rectangle
  *

libs/libvtrutil/src/vtr_geometry.h

@@ -9,6 +9,11 @@ circuits_dir=benchmarks/verilog
 # Path to directory of architectures to use
 archs_dir=arch/timing
 
+# Turned off the largest circuits since they sometimes cause the runtime of this
+# test to take too long.
+# circuit_list_add=LU32PEEng.v
+# circuit_list_add=mcml.v
+
 # Add circuits to list to sweep
 circuit_list_add=arm_core.v
 circuit_list_add=bgm.v
@@ -18,8 +23,6 @@ circuit_list_add=ch_intrinsics.v
 circuit_list_add=diffeq1.v
 circuit_list_add=diffeq2.v
 circuit_list_add=LU8PEEng.v
-#circuit_list_add=LU32PEEng.v
-#circuit_list_add=mcml.v
 circuit_list_add=mkDelayWorker32B.v
 circuit_list_add=mkPktMerge.v
 circuit_list_add=mkSMAdapter4B.v