Corrected broken pack pattern for carry chain specification in architecture file

git-svn-id: https://vtr-verilog-to-routing.googlecode.com/svn/trunk@4506 8e3573b8-cf2c-4f14-ef6d-137439e28b8b

Author: Jason Luu

vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml

@@ -260,6 +260,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
 						<direct name="direct1" input="lut5.in" output="lutpure.in">
 						</direct>
 						<direct name="direct2" input="lutpure.out" output="lut5.out">
+							<pack_pattern name="ble5" in_port="lutpure.out" out_port="lut5.out"/>
 						</direct>
 					</interconnect>
 				</mode>
@@ -343,6 +344,16 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
 				<direct name="direct5b" input="ble6.in_F" output="lut5[1:1].in[0:0]">
 				</direct>
 
+				<direct name="chain1" input="ble6.cin" output="lut5[0:0].cin">
+					<pack_pattern name="chain" in_port="ble6.cin" out_port="lut5[0:0].cin"/>
+				</direct>
+				<direct name="chain2" input="lut5[0:0].cout" output="lut5[1:1].cin">
+					<pack_pattern name="chain" in_port="lut5[0:0].cout" out_port="lut5[1:1].cin"/>
+				</direct>
+				<direct name="chain3" input="lut5[1:1].cout" output="ble6.cout">
+					<pack_pattern name="chain" in_port="lut5[1:1].cin" out_port="ble6.cout"/>
+				</direct>
+
 
 				<!--Clock -->  
 				<complete name="direct6" input="ble6.clk" output="ff.clk"/>