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patroupatrou
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operator benchmakrd added
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85 files changed

+1753
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‎ODIN_II/regression_test/benchmark/operators/binary_and.v

Lines changed: 25 additions & 0 deletions
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1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= a[0] & a[1];
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_and_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_and_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
0 1
6+
0 0
7+
0 1
8+
0 0
9+
0 1
10+
0 0
11+
1 1

‎ODIN_II/regression_test/benchmark/operators/binary_equal.v.disable

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= a[0] === a[1];
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_equal_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_and.v

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= a[0] && a[1];
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_and_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_and_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
0 1
6+
0 0
7+
0 1
8+
0 0
9+
0 1
10+
0 0
11+
1 1

‎ODIN_II/regression_test/benchmark/operators/binary_logical_equal.v

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= a[0] == a[1];
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_equal_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_equal_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
1 1
6+
1 0
7+
0 1
8+
0 0
9+
0 1
10+
0 0
11+
1 1

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_equal_than.v

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0:
22+
begin
23+
out <= (a[0] >= a[1]);
24+
end
25+
default: out <= 1'b0;
26+
endcase
27+
end
28+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_equal_than_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_equal_than_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
1 1
6+
1 0
7+
1 1
8+
1 0
9+
0 1
10+
0 0
11+
1 1

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_than.v

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= (a[0] > a[1]);
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_than_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_greater_than_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
0 1
6+
0 0
7+
1 1
8+
1 0
9+
0 1
10+
0 0
11+
0 1

‎ODIN_II/regression_test/benchmark/operators/binary_logical_less_equal_than.v

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= (a[0] <= a[1]);
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_less_equal_than_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

‎ODIN_II/regression_test/benchmark/operators/binary_logical_less_equal_than_output

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
out clk_out
2+
x 0
3+
0 1
4+
0 0
5+
1 1
6+
1 0
7+
0 1
8+
0 0
9+
1 1
10+
1 0
11+
1 1

‎ODIN_II/regression_test/benchmark/operators/binary_logical_less_than.v

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
module simple_op(
2+
clk,
3+
reset,
4+
a,
5+
out,
6+
clk_out
7+
);
8+
9+
input clk;
10+
input reset;
11+
input [1:0] a;
12+
13+
output out;
14+
output clk_out;
15+
16+
assign clk_out = clk;
17+
18+
always @(posedge clk)
19+
begin
20+
case(reset)
21+
1'b0: out <= (a[0] < a[1]);
22+
default: out <= 1'b0;
23+
endcase
24+
end
25+
endmodule

‎ODIN_II/regression_test/benchmark/operators/binary_logical_less_than_input

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
GLOBAL_SIM_BASE_CLK clk reset a
2+
0 0 1 0X0
3+
0 1 1 0X0
4+
0 0 0 0X0
5+
0 1 0 0X0
6+
0 0 0 0X1
7+
0 1 0 0X1
8+
0 0 0 0X2
9+
0 1 0 0X2
10+
0 0 0 0X3
11+
0 1 0 0X3

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