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vaughnbetzvaughnbetz
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Merge branch 'master' into append-link-flags
2 parents bcf9336 + 45bf4c9 commit 6e2f39e

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3 files changed

+34
-32
lines changed

3 files changed

+34
-32
lines changed

‎libs/libvtrcapnproto/CMakeLists.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
include(GNUInstallDirs)
2+
13
if(NOT MSCV)
24
# These flags generate noisy but non-bug warnings when using lib kj,
35
# supress them.
@@ -28,7 +30,7 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS
2830
${CAPNP_DEFS}
2931
)
3032

31-
install(FILES ${CAPNP_DEFS} DESTINATION capnp)
33+
install(FILES ${CAPNP_DEFS} DESTINATION ${CMAKE_INSTALL_DATADIR}/vtr)
3234

3335
add_library(libvtrcapnproto STATIC
3436
${CAPNP_SRCS}

‎vpr/src/route/rr_graph_uxsdcxx_serializer.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1479,8 +1479,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
14791479
correct_string += get_arch_file_name();
14801480
if (correct_string != tool_comment) {
14811481
VTR_LOG("\n");
1482-
VTR_LOG_WARN("This RR graph file is based on %s while your input architecture file is %s compatability issues may arise\n",
1483-
get_arch_file_name(), tool_comment);
1482+
VTR_LOG_WARN("This RR graph file is %s while your input architecture file is %s, compatibility issues may arise\n",
1483+
tool_comment, get_arch_file_name());
14841484
VTR_LOG("\n");
14851485
}
14861486
}
@@ -1489,8 +1489,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
14891489
inline void set_rr_graph_tool_version(const char* tool_version, void*& /*ctx*/) final {
14901490
if (strcmp(tool_version, vtr::VERSION) != 0) {
14911491
VTR_LOG("\n");
1492-
VTR_LOG_WARN("This architecture version is for VPR %s while your current VPR version is %s compatability issues may arise\n",
1493-
vtr::VERSION, tool_version);
1492+
VTR_LOG_WARN("This architecture version is for VPR %s while your current VPR version is %s, compatibility issues may arise\n",
1493+
tool_version, vtr::VERSION);
14941494
VTR_LOG("\n");
14951495
}
14961496
}

‎vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -894,8 +894,8 @@
894894
</direct>
895895
</interconnect>
896896
</mode>
897-
<mode name="mem_2048x8_dp">
898-
<pb_type name="mem_2048x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
897+
<mode name="mem_4096x8_dp">
898+
<pb_type name="mem_4096x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
899899
<input name="addr1" num_pins="12" port_class="address1"/>
900900
<input name="addr2" num_pins="12" port_class="address2"/>
901901
<input name="data1" num_pins="8" port_class="data_in1"/>
@@ -905,45 +905,45 @@
905905
<output name="out1" num_pins="8" port_class="data_out1"/>
906906
<output name="out2" num_pins="8" port_class="data_out2"/>
907907
<clock name="clk" num_pins="1" port_class="clock"/>
908-
<T_setup value="509e-12" port="mem_2048x8_dp.addr1" clock="clk"/>
909-
<T_setup value="509e-12" port="mem_2048x8_dp.data1" clock="clk"/>
910-
<T_setup value="509e-12" port="mem_2048x8_dp.we1" clock="clk"/>
911-
<T_setup value="509e-12" port="mem_2048x8_dp.addr2" clock="clk"/>
912-
<T_setup value="509e-12" port="mem_2048x8_dp.data2" clock="clk"/>
913-
<T_setup value="509e-12" port="mem_2048x8_dp.we2" clock="clk"/>
914-
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out1" clock="clk"/>
915-
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out2" clock="clk"/>
908+
<T_setup value="509e-12" port="mem_4096x8_dp.addr1" clock="clk"/>
909+
<T_setup value="509e-12" port="mem_4096x8_dp.data1" clock="clk"/>
910+
<T_setup value="509e-12" port="mem_4096x8_dp.we1" clock="clk"/>
911+
<T_setup value="509e-12" port="mem_4096x8_dp.addr2" clock="clk"/>
912+
<T_setup value="509e-12" port="mem_4096x8_dp.data2" clock="clk"/>
913+
<T_setup value="509e-12" port="mem_4096x8_dp.we2" clock="clk"/>
914+
<T_clock_to_Q max="1.234e-9" port="mem_4096x8_dp.out1" clock="clk"/>
915+
<T_clock_to_Q max="1.234e-9" port="mem_4096x8_dp.out2" clock="clk"/>
916916
<power method="pin-toggle">
917917
<port name="clk" energy_per_toggle="17.9e-12"/>
918918
<static_power power_per_instance="0.0"/>
919919
</power>
920920
</pb_type>
921921
<interconnect>
922-
<direct name="address1" input="memory.addr1[11:0]" output="mem_2048x8_dp.addr1">
923-
<delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_2048x8_dp.addr1"/>
922+
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_dp.addr1">
923+
<delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_dp.addr1"/>
924924
</direct>
925-
<direct name="address2" input="memory.addr2[11:0]" output="mem_2048x8_dp.addr2">
926-
<delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_2048x8_dp.addr2"/>
925+
<direct name="address2" input="memory.addr2[11:0]" output="mem_4096x8_dp.addr2">
926+
<delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_4096x8_dp.addr2"/>
927927
</direct>
928-
<direct name="data1" input="memory.data[7:0]" output="mem_2048x8_dp.data1">
929-
<delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_2048x8_dp.data1"/>
928+
<direct name="data1" input="memory.data[7:0]" output="mem_4096x8_dp.data1">
929+
<delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_dp.data1"/>
930930
</direct>
931-
<direct name="data2" input="memory.data[15:8]" output="mem_2048x8_dp.data2">
932-
<delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_2048x8_dp.data2"/>
931+
<direct name="data2" input="memory.data[15:8]" output="mem_4096x8_dp.data2">
932+
<delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_4096x8_dp.data2"/>
933933
</direct>
934-
<direct name="writeen1" input="memory.we1" output="mem_2048x8_dp.we1">
935-
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x8_dp.we1"/>
934+
<direct name="writeen1" input="memory.we1" output="mem_4096x8_dp.we1">
935+
<delay_constant max="132e-12" in_port="memory.we1" out_port="mem_4096x8_dp.we1"/>
936936
</direct>
937-
<direct name="writeen2" input="memory.we2" output="mem_2048x8_dp.we2">
938-
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x8_dp.we2"/>
937+
<direct name="writeen2" input="memory.we2" output="mem_4096x8_dp.we2">
938+
<delay_constant max="132e-12" in_port="memory.we2" out_port="mem_4096x8_dp.we2"/>
939939
</direct>
940-
<direct name="dataout1" input="mem_2048x8_dp.out1" output="memory.out[7:0]">
941-
<delay_constant max="40e-12" in_port="mem_2048x8_dp.out1" out_port="memory.out[7:0]"/>
940+
<direct name="dataout1" input="mem_4096x8_dp.out1" output="memory.out[7:0]">
941+
<delay_constant max="40e-12" in_port="mem_4096x8_dp.out1" out_port="memory.out[7:0]"/>
942942
</direct>
943-
<direct name="dataout2" input="mem_2048x8_dp.out2" output="memory.out[15:8]">
944-
<delay_constant max="40e-12" in_port="mem_2048x8_dp.out2" out_port="memory.out[15:8]"/>
943+
<direct name="dataout2" input="mem_4096x8_dp.out2" output="memory.out[15:8]">
944+
<delay_constant max="40e-12" in_port="mem_4096x8_dp.out2" out_port="memory.out[15:8]"/>
945945
</direct>
946-
<direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
946+
<direct name="clk" input="memory.clk" output="mem_4096x8_dp.clk">
947947
</direct>
948948
</interconnect>
949949
</mode>

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