updage strong odin golden result

Author: amin1377

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt

@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	5.41	vpr	210.32 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215372	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583141	0.000535113	0.00311475	0.00261673	8	12	5	72000	72000	5593.62	349.601	2.10	0.0862302	0.0767113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109455	0.00960207	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	7.10	vpr	394.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	403912	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.6 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000585834	0.000538181	0.00313704	0.0026163	8	12	5	72000	72000	5593.62	349.601	2.10	0.0854666	0.0759832	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110022	0.00964644	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.33	vpr	210.00 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215036	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.7 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000588315	0.000539577	0.00308844	0.0026033	8	12	5	72000	72000	5593.62	349.601	2.09	0.0840539	0.0747826	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0100088	0.0087372	

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	4.81	vpr	207.77 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	212752	2	2	22	24	2	4	6	4	4	16	clb	auto	51.5 MiB	0.10	4	15	2	10	3	192.8 MiB	0.02	0.00	1.297	0	0	1.297	0.49	0.000472548	0.000433891	0.00258794	0.00211333	4	6	2	72000	36000	2827.54	176.721	1.75	0.0226752	0.0196524	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00604643	0.0051332	

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt

@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	2.93	vpr	373.06 MiB		0.14	20488	-1	-1	1	0.02	-1	-1	33464	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	382012	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000175279	0.000165491	0.000976401	0.000767979	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00449048	0.00368003	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.73 MiB		0.14	20620	-1	-1	1	0.02	-1	-1	33596	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193264	2	1	3	4	1	3	4	3	3	9	-1	auto	49.8 MiB	0.02	6	9	3	3	3	184.7 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000179683	0.000169331	0.00104574	0.000777636	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00434022	0.00346833	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.69	odin	761.83 MiB		14.13	780112	-1	-1	2	1.41	-1	-1	54088	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335516	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.21	22	86316	62090	3287	20939	314.4 MiB	8.27	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426637	0.00401077	0.352304	0.330517	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.426089	0.399481	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.85	odin	761.64 MiB		14.27	779924	-1	-1	2	1.37	-1	-1	54552	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336112	5	156	191	347	1	163	316	15	15	225	clb	auto	71.9 MiB	1.14	25	86316	61881	3554	20881	315.0 MiB	8.35	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00427632	0.00401248	0.356421	0.332972	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.438475	0.409721	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.72	vpr	218.05 MiB		2.19	38292	-1	-1	1	0.02	-1	-1	33576	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223280	2	1	3	4	1	3	4	3	3	9	-1	auto	76.3 MiB	0.03	4	9	3	5	1	213.1 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000167702	0.000158607	0.000975812	0.00076565	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428013	0.00347708	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.85	vpr	218.27 MiB		2.22	38424	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223504	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000179672	0.000169578	0.00106215	0.000790093	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00420473	0.00335158	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.92	odin	592.27 MiB		9.47	606488	-1	-1	2	0.15	-1	-1	37288	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550084	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	10.51	8852	208372	78139	120196	10037	513.9 MiB	41.04	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.112519	0.10601	11.801	11.1176	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.09	15.7544	14.9174	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.57	odin	592.08 MiB		9.49	606288	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553212	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.1 MiB	10.54	8741	214546	82147	122429	9970	513.6 MiB	42.17	0.47	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112604	0.106159	12.0753	11.3955	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.66	16.4333	15.5853	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939