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[read_xml] revert new changes
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libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 63 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -306,20 +306,20 @@ static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc
306306
/* Added for vib_layout*/
307307
static void ProcessVibLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data);
308308

309-
static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer);
310-
311309
/* Added for vib_layout*/
312310
static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer);
313311

314-
static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data);
315-
316312
/* Added for vib_layout*/
317313
static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def,
318314
int die_number,
319315
vtr::string_internment& strings,
320316
pugi::xml_node layout_block_type_tag,
321317
const pugiutil::loc_data& loc_data);
322318

319+
320+
static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer);
321+
static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data);
322+
323323
static int get_number_of_layers(pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data);
324324
static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data);
325325

@@ -750,10 +750,15 @@ static void LoadPinLoc(pugi::xml_node Locations,
750750
&sub_tile,
751751
token.c_str(),
752752
loc_data);
753-
753+
/* Get the offset in the capacity range */
754+
auto capacity_range = ProcessInstanceString<t_sub_tile*>(Locations,
755+
&sub_tile,
756+
token.c_str(),
757+
loc_data);
758+
VTR_ASSERT(0 <= capacity_range.first && capacity_range.second < sub_tile_capacity);
754759
for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) {
755760
VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity);
756-
for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) {
761+
for (int capacity = capacity_range.first; capacity <= capacity_range.second; ++capacity) {
757762
int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity;
758763
int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index];
759764
type->pinloc[width][height][side][physical_pin_index] = true;
@@ -3572,8 +3577,8 @@ static void ProcessPinLocations(pugi::xml_node Locations,
35723577

35733578
//Verify that all top-level pins have had their locations specified
35743579

3575-
//Record all the specified pins
3576-
std::map<std::string, std::set<int>> port_pins_with_specified_locations;
3580+
//Record all the specified pins, (capacity, port_name, index)
3581+
std::map<int, std::map<std::string, std::set<int>>> port_pins_with_specified_locations;
35773582
for (int l = 0; l < num_of_avail_layer; ++l) {
35783583
for (int w = 0; w < PhysicalTileType->width; ++w) {
35793584
for (int h = 0; h < PhysicalTileType->height; ++h) {
@@ -3634,9 +3639,11 @@ static void ProcessPinLocations(pugi::xml_node Locations,
36343639
VTR_ASSERT(pin_low_idx >= 0);
36353640
VTR_ASSERT(pin_high_idx >= 0);
36363641

3637-
for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) {
3638-
//Record that the pin has its location specified
3639-
port_pins_with_specified_locations[inst_port.port_name()].insert(ipin);
3642+
for (int iinst = inst_lsb + SubTile->capacity.low; iinst <= inst_msb + SubTile->capacity.low; ++iinst) {
3643+
for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) {
3644+
//Record that the pin has it's location specified
3645+
port_pins_with_specified_locations[iinst][inst_port.port_name()].insert(ipin);
3646+
}
36403647
}
36413648
}
36423649
}
@@ -3645,13 +3652,15 @@ static void ProcessPinLocations(pugi::xml_node Locations,
36453652
}
36463653

36473654
//Check for any pins missing location specs
3648-
for (const auto& port : SubTile->ports) {
3649-
for (int ipin = 0; ipin < port.num_pins; ++ipin) {
3650-
if (!port_pins_with_specified_locations[port.name].count(ipin)) {
3651-
//Missing
3652-
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
3653-
"Pin '%s.%s[%d]' has no pin location specified (a location is required for pattern=\"custom\")",
3654-
SubTile->name.c_str(), port.name, ipin);
3655+
for (int iinst = SubTile->capacity.low; iinst < SubTile->capacity.high; ++iinst) {
3656+
for (const auto& port : SubTile->ports) {
3657+
for (int ipin = 0; ipin < port.num_pins; ++ipin) {
3658+
if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) {
3659+
//Missing
3660+
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
3661+
"Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")",
3662+
SubTile->name.c_str(), iinst, port.name, ipin);
3663+
}
36553664
}
36563665
}
36573666
}
@@ -3960,6 +3969,7 @@ static std::vector<t_segment_inf> ProcessSegments(pugi::xml_node Parent,
39603969

39613970
//Unidir requires the following tags
39623971
expected_subtags.emplace_back("mux");
3972+
expected_subtags.emplace_back("bend");
39633973
expected_subtags.emplace_back("mux_inter_die");
39643974
//with the following two tags, we can allow the architecture file to define
39653975
//different muxes with different delays for wires with different directions
@@ -4117,39 +4127,6 @@ static std::vector<t_segment_inf> ProcessSegments(pugi::xml_node Parent,
41174127
return Segs;
41184128
}
41194129

4120-
static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb) {
4121-
auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL);
4122-
auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL);
4123-
4124-
auto starty_attr = get_attribute(SubElem, "starty", loc_data, ReqOpt::OPTIONAL);
4125-
auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL);
4126-
4127-
auto repeatx_attr = get_attribute(SubElem, "repeatx", loc_data, ReqOpt::OPTIONAL);
4128-
auto repeaty_attr = get_attribute(SubElem, "repeaty", loc_data, ReqOpt::OPTIONAL);
4129-
4130-
auto incrx_attr = get_attribute(SubElem, "incrx", loc_data, ReqOpt::OPTIONAL);
4131-
auto incry_attr = get_attribute(SubElem, "incry", loc_data, ReqOpt::OPTIONAL);
4132-
4133-
//parse the values from the architecture file and fill out SB region information
4134-
vtr::FormulaParser p;
4135-
4136-
vtr::t_formula_data vars;
4137-
vars.set_var_value("W", grid_width);
4138-
vars.set_var_value("H", grid_height);
4139-
4140-
sb.reg_x.start = startx_attr.empty() ? 0 : p.parse_formula(startx_attr.value(), vars);
4141-
sb.reg_y.start = starty_attr.empty() ? 0 : p.parse_formula(starty_attr.value(), vars);
4142-
4143-
sb.reg_x.end = endx_attr.empty() ? (grid_width - 1) : p.parse_formula(endx_attr.value(), vars);
4144-
sb.reg_y.end = endy_attr.empty() ? (grid_height - 1) : p.parse_formula(endy_attr.value(), vars);
4145-
4146-
sb.reg_x.repeat = repeatx_attr.empty() ? 0 : p.parse_formula(repeatx_attr.value(), vars);
4147-
sb.reg_y.repeat = repeaty_attr.empty() ? 0 : p.parse_formula(repeaty_attr.value(), vars);
4148-
4149-
sb.reg_x.incr = incrx_attr.empty() ? 1 : p.parse_formula(incrx_attr.value(), vars);
4150-
sb.reg_y.incr = incry_attr.empty() ? 1 : p.parse_formula(incry_attr.value(), vars);
4151-
}
4152-
41534130
static void ProcessBend(pugi::xml_node Node, std::vector<int>& list, std::vector<int>& part_len, bool& isbend, const int len, const pugiutil::loc_data& loc_data) {
41544131
const char* tmp = nullptr;
41554132
int i;
@@ -4223,6 +4200,41 @@ static void ProcessBend(pugi::xml_node Node, std::vector<int>& list, std::vector
42234200
part_len.push_back(list.size() + 1 - sum_len);
42244201
}
42254202

4203+
static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb){
4204+
auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL);
4205+
auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL);
4206+
4207+
auto starty_attr = get_attribute(SubElem, "starty", loc_data, ReqOpt::OPTIONAL);
4208+
auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL);
4209+
4210+
auto repeatx_attr = get_attribute(SubElem, "repeatx", loc_data, ReqOpt::OPTIONAL);
4211+
auto repeaty_attr = get_attribute(SubElem, "repeaty", loc_data, ReqOpt::OPTIONAL);
4212+
4213+
auto incrx_attr = get_attribute(SubElem, "incrx", loc_data, ReqOpt::OPTIONAL);
4214+
auto incry_attr = get_attribute(SubElem, "incry", loc_data, ReqOpt::OPTIONAL);
4215+
4216+
//parse the values from the architecture file and fill out SB region information
4217+
vtr::FormulaParser p;
4218+
4219+
vtr::t_formula_data vars;
4220+
vars.set_var_value("W", grid_width);
4221+
vars.set_var_value("H", grid_height);
4222+
4223+
4224+
sb.reg_x.start = startx_attr.empty() ? 0 : p.parse_formula(startx_attr.value(), vars);
4225+
sb.reg_y.start = starty_attr.empty() ? 0 : p.parse_formula(starty_attr.value(), vars);
4226+
4227+
sb.reg_x.end = endx_attr.empty() ? (grid_width - 1) : p.parse_formula(endx_attr.value(), vars);
4228+
sb.reg_y.end = endy_attr.empty() ? (grid_height -1) : p.parse_formula(endy_attr.value(), vars);
4229+
4230+
sb.reg_x.repeat = repeatx_attr.empty() ? 0 : p.parse_formula(repeatx_attr.value(), vars);
4231+
sb.reg_y.repeat = repeaty_attr.empty() ? 0 : p.parse_formula(repeaty_attr.value(), vars);
4232+
4233+
sb.reg_x.incr = incrx_attr.empty() ? 1 : p.parse_formula(incrx_attr.value(), vars);
4234+
sb.reg_y.incr = incry_attr.empty() ? 1 : p.parse_formula(incry_attr.value(), vars);
4235+
4236+
}
4237+
42264238
/* Processes the switchblocklist section from the xml architecture file.
42274239
* See vpr/SRC/route/build_switchblocks.c for a detailed description of this
42284240
* switch block format */

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