@@ -306,20 +306,20 @@ static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc
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/* Added for vib_layout*/
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static void ProcessVibLayout (pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data);
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- static t_grid_def ProcessGridLayout (vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int & num_of_avail_layer);
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-
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/* Added for vib_layout*/
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static t_vib_grid_def ProcessVibGridLayout (vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int & num_of_avail_layer);
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- static void ProcessBlockTypeLocs (t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data);
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-
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/* Added for vib_layout*/
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static void ProcessVibBlockTypeLocs (t_vib_grid_def& grid_def,
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int die_number,
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vtr::string_internment& strings,
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pugi::xml_node layout_block_type_tag,
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const pugiutil::loc_data& loc_data);
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+
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+ static t_grid_def ProcessGridLayout (vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int & num_of_avail_layer);
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+ static void ProcessBlockTypeLocs (t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data);
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+
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static int get_number_of_layers (pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data);
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static void ProcessDevice (pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data);
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@@ -750,10 +750,15 @@ static void LoadPinLoc(pugi::xml_node Locations,
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&sub_tile,
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token.c_str (),
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loc_data);
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-
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+ /* Get the offset in the capacity range */
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+ auto capacity_range = ProcessInstanceString<t_sub_tile*>(Locations,
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+ &sub_tile,
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+ token.c_str (),
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+ loc_data);
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+ VTR_ASSERT (0 <= capacity_range.first && capacity_range.second < sub_tile_capacity);
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for (int pin_num = pin_range.first ; pin_num < pin_range.second ; ++pin_num) {
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VTR_ASSERT (pin_num < (int )sub_tile.sub_tile_to_tile_pin_indices .size () / sub_tile_capacity);
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- for (int capacity = 0 ; capacity < sub_tile_capacity ; ++capacity) {
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+ for (int capacity = capacity_range. first ; capacity <= capacity_range. second ; ++capacity) {
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int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity;
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int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices [sub_tile_pin_index];
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type->pinloc [width][height][side][physical_pin_index] = true ;
@@ -3572,8 +3577,8 @@ static void ProcessPinLocations(pugi::xml_node Locations,
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// Verify that all top-level pins have had their locations specified
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- // Record all the specified pins
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- std::map<std::string, std::set<int >> port_pins_with_specified_locations;
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+ // Record all the specified pins, (capacity, port_name, index)
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+ std::map<int , std::map<std:: string, std::set<int > >> port_pins_with_specified_locations;
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for (int l = 0 ; l < num_of_avail_layer; ++l) {
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for (int w = 0 ; w < PhysicalTileType->width ; ++w) {
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for (int h = 0 ; h < PhysicalTileType->height ; ++h) {
@@ -3634,9 +3639,11 @@ static void ProcessPinLocations(pugi::xml_node Locations,
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VTR_ASSERT (pin_low_idx >= 0 );
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VTR_ASSERT (pin_high_idx >= 0 );
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- for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) {
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- // Record that the pin has its location specified
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- port_pins_with_specified_locations[inst_port.port_name ()].insert (ipin);
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+ for (int iinst = inst_lsb + SubTile->capacity .low ; iinst <= inst_msb + SubTile->capacity .low ; ++iinst) {
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+ for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) {
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+ // Record that the pin has it's location specified
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+ port_pins_with_specified_locations[iinst][inst_port.port_name ()].insert (ipin);
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+ }
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}
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}
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}
@@ -3645,13 +3652,15 @@ static void ProcessPinLocations(pugi::xml_node Locations,
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}
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// Check for any pins missing location specs
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- for (const auto & port : SubTile->ports ) {
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- for (int ipin = 0 ; ipin < port.num_pins ; ++ipin) {
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- if (!port_pins_with_specified_locations[port.name ].count (ipin)) {
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- // Missing
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- archfpga_throw (loc_data.filename_c_str (), loc_data.line (Locations),
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- " Pin '%s.%s[%d]' has no pin location specified (a location is required for pattern=\" custom\" )" ,
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- SubTile->name .c_str (), port.name , ipin);
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+ for (int iinst = SubTile->capacity .low ; iinst < SubTile->capacity .high ; ++iinst) {
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+ for (const auto & port : SubTile->ports ) {
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+ for (int ipin = 0 ; ipin < port.num_pins ; ++ipin) {
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+ if (!port_pins_with_specified_locations[iinst][port.name ].count (ipin)) {
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+ // Missing
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+ archfpga_throw (loc_data.filename_c_str (), loc_data.line (Locations),
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+ " Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\" custom\" )" ,
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+ SubTile->name .c_str (), iinst, port.name , ipin);
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+ }
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}
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}
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}
@@ -3960,6 +3969,7 @@ static std::vector<t_segment_inf> ProcessSegments(pugi::xml_node Parent,
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// Unidir requires the following tags
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expected_subtags.emplace_back (" mux" );
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+ expected_subtags.emplace_back (" bend" );
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expected_subtags.emplace_back (" mux_inter_die" );
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// with the following two tags, we can allow the architecture file to define
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// different muxes with different delays for wires with different directions
@@ -4117,39 +4127,6 @@ static std::vector<t_segment_inf> ProcessSegments(pugi::xml_node Parent,
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return Segs;
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}
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- static void calculate_custom_SB_locations (const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb) {
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- auto startx_attr = get_attribute (SubElem, " startx" , loc_data, ReqOpt::OPTIONAL);
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- auto endx_attr = get_attribute (SubElem, " endx" , loc_data, ReqOpt::OPTIONAL);
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-
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- auto starty_attr = get_attribute (SubElem, " starty" , loc_data, ReqOpt::OPTIONAL);
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- auto endy_attr = get_attribute (SubElem, " endy" , loc_data, ReqOpt::OPTIONAL);
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-
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- auto repeatx_attr = get_attribute (SubElem, " repeatx" , loc_data, ReqOpt::OPTIONAL);
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- auto repeaty_attr = get_attribute (SubElem, " repeaty" , loc_data, ReqOpt::OPTIONAL);
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-
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- auto incrx_attr = get_attribute (SubElem, " incrx" , loc_data, ReqOpt::OPTIONAL);
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- auto incry_attr = get_attribute (SubElem, " incry" , loc_data, ReqOpt::OPTIONAL);
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-
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- // parse the values from the architecture file and fill out SB region information
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- vtr::FormulaParser p;
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-
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- vtr::t_formula_data vars;
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- vars.set_var_value (" W" , grid_width);
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- vars.set_var_value (" H" , grid_height);
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-
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- sb.reg_x .start = startx_attr.empty () ? 0 : p.parse_formula (startx_attr.value (), vars);
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- sb.reg_y .start = starty_attr.empty () ? 0 : p.parse_formula (starty_attr.value (), vars);
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-
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- sb.reg_x .end = endx_attr.empty () ? (grid_width - 1 ) : p.parse_formula (endx_attr.value (), vars);
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- sb.reg_y .end = endy_attr.empty () ? (grid_height - 1 ) : p.parse_formula (endy_attr.value (), vars);
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-
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- sb.reg_x .repeat = repeatx_attr.empty () ? 0 : p.parse_formula (repeatx_attr.value (), vars);
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- sb.reg_y .repeat = repeaty_attr.empty () ? 0 : p.parse_formula (repeaty_attr.value (), vars);
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-
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- sb.reg_x .incr = incrx_attr.empty () ? 1 : p.parse_formula (incrx_attr.value (), vars);
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- sb.reg_y .incr = incry_attr.empty () ? 1 : p.parse_formula (incry_attr.value (), vars);
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- }
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-
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static void ProcessBend (pugi::xml_node Node, std::vector<int >& list, std::vector<int >& part_len, bool & isbend, const int len, const pugiutil::loc_data& loc_data) {
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const char * tmp = nullptr ;
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int i;
@@ -4223,6 +4200,41 @@ static void ProcessBend(pugi::xml_node Node, std::vector<int>& list, std::vector
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part_len.push_back (list.size () + 1 - sum_len);
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}
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+ static void calculate_custom_SB_locations (const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb){
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+ auto startx_attr = get_attribute (SubElem, " startx" , loc_data, ReqOpt::OPTIONAL);
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+ auto endx_attr = get_attribute (SubElem, " endx" , loc_data, ReqOpt::OPTIONAL);
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+
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+ auto starty_attr = get_attribute (SubElem, " starty" , loc_data, ReqOpt::OPTIONAL);
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+ auto endy_attr = get_attribute (SubElem, " endy" , loc_data, ReqOpt::OPTIONAL);
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+
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+ auto repeatx_attr = get_attribute (SubElem, " repeatx" , loc_data, ReqOpt::OPTIONAL);
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+ auto repeaty_attr = get_attribute (SubElem, " repeaty" , loc_data, ReqOpt::OPTIONAL);
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+
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+ auto incrx_attr = get_attribute (SubElem, " incrx" , loc_data, ReqOpt::OPTIONAL);
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+ auto incry_attr = get_attribute (SubElem, " incry" , loc_data, ReqOpt::OPTIONAL);
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+
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+ // parse the values from the architecture file and fill out SB region information
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+ vtr::FormulaParser p;
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+
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+ vtr::t_formula_data vars;
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+ vars.set_var_value (" W" , grid_width);
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+ vars.set_var_value (" H" , grid_height);
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+
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+
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+ sb.reg_x .start = startx_attr.empty () ? 0 : p.parse_formula (startx_attr.value (), vars);
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+ sb.reg_y .start = starty_attr.empty () ? 0 : p.parse_formula (starty_attr.value (), vars);
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+
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+ sb.reg_x .end = endx_attr.empty () ? (grid_width - 1 ) : p.parse_formula (endx_attr.value (), vars);
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+ sb.reg_y .end = endy_attr.empty () ? (grid_height -1 ) : p.parse_formula (endy_attr.value (), vars);
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+
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+ sb.reg_x .repeat = repeatx_attr.empty () ? 0 : p.parse_formula (repeatx_attr.value (), vars);
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+ sb.reg_y .repeat = repeaty_attr.empty () ? 0 : p.parse_formula (repeaty_attr.value (), vars);
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+
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+ sb.reg_x .incr = incrx_attr.empty () ? 1 : p.parse_formula (incrx_attr.value (), vars);
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+ sb.reg_y .incr = incry_attr.empty () ? 1 : p.parse_formula (incry_attr.value (), vars);
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+
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+ }
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+
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/* Processes the switchblocklist section from the xml architecture file.
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* See vpr/SRC/route/build_switchblocks.c for a detailed description of this
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* switch block format */
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