vpr: fix regression test issues related to heterogeneous tiles

acomodi · acomodi · commit 681c32fd5ad1 · 2020-03-27T20:39:55.000+01:00
There still are two regression tests which are not passing

Signed-off-by: Alessandro Comodi &lt;acomodi@antmicro.com&gt;
diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -59,7 +59,6 @@ struct t_equivalent_site;
 struct t_physical_tile_type;
 typedef const t_physical_tile_type* t_physical_tile_type_ptr;
 struct t_sub_tile;
-struct t_capacity_range;
 struct t_logical_block_type;
 typedef const t_logical_block_type* t_logical_block_type_ptr;
 struct t_logical_pin;
@@ -447,6 +446,12 @@ struct t_class {
     std::vector<int> pinlist; /* [0..num_pins - 1] */
 };
 
+/* Struct to hold the class ranges for specific sub tiles */
+struct t_class_range {
+    int low = 0;
+    int high = 0;
+};
+
 enum e_power_wire_type {
     POWER_WIRE_TYPE_UNDEFINED = 0,
     POWER_WIRE_TYPE_IGNORED,
@@ -636,11 +641,9 @@ struct t_physical_tile_type {
  * Totale TILE_X capacity is 17
  */
 struct t_capacity_range {
-  private:
     int low = 0;
     int high = 0;
 
-  public:
     void set(int low_cap, int high_cap) {
         low = low_cap;
         high = high_cap;
@@ -670,6 +673,7 @@ struct t_sub_tile {
     std::vector<t_logical_block_type_ptr> equivalent_sites;
 
     t_capacity_range capacity;
+    t_class_range class_range;
 
     int num_phy_pins = 0;
 
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -480,9 +480,13 @@ static void SetupPinClasses(t_physical_tile_type* PhysicalTileType) {
 
     pin_count = 0;
 
+    t_class_range class_range;
+
     /* Equivalent pins share the same class, non-equivalent pins belong to different pin classes */
     for (auto& sub_tile : PhysicalTileType->sub_tiles) {
         int capacity = sub_tile.capacity.total();
+        class_range.low = PhysicalTileType->class_inf.size();
+        class_range.high = class_range.low - 1;
         for (i = 0; i < capacity; ++i) {
             for (const auto& port : sub_tile.ports) {
                 if (port.equivalent != PortEquivalence::NONE) {
@@ -511,12 +515,14 @@ static void SetupPinClasses(t_physical_tile_type* PhysicalTileType) {
                     }
 
                     PhysicalTileType->class_inf.push_back(class_inf);
+                    class_range.high++;
                 } else if (port.equivalent == PortEquivalence::NONE) {
                     for (k = 0; k < port.num_pins; ++k) {
                         t_class class_inf;
                         num_class = (int)PhysicalTileType->class_inf.size();
                         class_inf.num_pins = 1;
                         class_inf.pinlist.push_back(pin_count);
+                        class_inf.equivalence = port.equivalent;
 
                         if (port.type == IN_PORT) {
                             class_inf.type = RECEIVER;
@@ -535,10 +541,15 @@ static void SetupPinClasses(t_physical_tile_type* PhysicalTileType) {
                         pin_count++;
 
                         PhysicalTileType->class_inf.push_back(class_inf);
+                        class_range.high++;
                     }
                 }
             }
         }
+
+        PhysicalTileType->sub_tiles[sub_tile.index].class_range = class_range;
+
+        VTR_LOG("PHYSICAL TILE: %s\n\tCAPACITY: %d\n\tCLASS RANGE: LOW %d, HIGH %d\n\n", PhysicalTileType->name, PhysicalTileType->capacity, PhysicalTileType->sub_tiles[sub_tile.index].class_range.low, PhysicalTileType->sub_tiles[sub_tile.index].class_range.high);
     }
 
     VTR_ASSERT(pin_count == PhysicalTileType->num_pins);
@@ -1933,12 +1944,11 @@ static void Process_Fc(pugi::xml_node Node,
 
     /* Go through all the port/segment combinations and create the (potentially
      * overriden) pin/seg Fc specifications */
-    int pins_per_capacity_instance = pin_counts.total() / SubTile->capacity.total();
     for (size_t iseg = 0; iseg < segments.size(); ++iseg) {
         for (int icapacity = 0; icapacity < SubTile->capacity.total(); ++icapacity) {
             //If capacity > 0, we need t offset the block index by the number of pins per instance
             //this ensures that all pins have an Fc specification
-            int iblk_pin = icapacity * pins_per_capacity_instance;
+            int iblk_pin = icapacity * pin_counts.total();
 
             for (const auto& port : SubTile->ports) {
                 t_fc_specification fc_spec;
@@ -2004,6 +2014,7 @@ static void Process_Fc(pugi::xml_node Node,
                     //XXX: this assumes that iterating through the tile ports
                     //     in order yields the block pin order
                     int true_physical_blk_pin = SubTile->sub_tile_to_tile_pin_indices[iblk_pin];
+                    VTR_LOG("PHYSICAL PIN: %d\n", true_physical_blk_pin);
                     fc_spec.pins.push_back(true_physical_blk_pin);
                     ++iblk_pin;
                 }
@@ -3001,7 +3012,7 @@ static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent,
         if (port.type == IN_PORT && port.is_clock == false) {
             pin_counts.input += port.num_pins;
         } else if (port.type == OUT_PORT) {
-            pin_counts.output = port.num_pins;
+            pin_counts.output += port.num_pins;
         } else {
             VTR_ASSERT(port.is_clock && port.type == IN_PORT);
             pin_counts.clock += port.num_pins;
@@ -3440,7 +3451,7 @@ static void ProcessSubTiles(pugi::xml_node Node,
         SubTile.name = name;
 
         /* Load properties */
-        unsigned int capacity = get_attribute(CurSubTile, "capacity", loc_data, ReqOpt::OPTIONAL).as_uint(1);
+        int capacity = get_attribute(CurSubTile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1);
         SubTile.capacity.set(PhysicalTileType->capacity, capacity - 1);
         PhysicalTileType->capacity += capacity;
 
@@ -3450,16 +3461,16 @@ static void ProcessSubTiles(pugi::xml_node Node,
         /* Map Sub Tile physical pins with the Physical Tile Type physical pins.
          * This takes into account the capacity of each sub tiles to add the correct offset.
          */
-        for (int ipin = 0; ipin < (int)capacity * pin_counts.total(); ipin++) {
+        for (int ipin = 0; ipin < capacity * pin_counts.total(); ipin++) {
             SubTile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin);
         }
 
         SubTile.num_phy_pins = pin_counts.total() * capacity;
 
         /* Assign pin counts to the Physical Tile Type */
-        PhysicalTileType->num_input_pins += capacity * pin_counts.input;
-        PhysicalTileType->num_output_pins += capacity * pin_counts.output;
-        PhysicalTileType->num_clock_pins += capacity * pin_counts.clock;
+        PhysicalTileType->num_input_pins += pin_counts.input;
+        PhysicalTileType->num_output_pins += pin_counts.output;
+        PhysicalTileType->num_clock_pins += pin_counts.clock;
         PhysicalTileType->num_pins += capacity * pin_counts.total();
         PhysicalTileType->num_inst_pins += pin_counts.total();
 
diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp
@@ -250,7 +250,7 @@ void read_user_pad_loc(const char* pad_loc_file) {
 
         auto physical_tile = device_ctx.grid[i][j].type;
         auto logical_block = cluster_ctx.clb_nlist.block_type(bnum);
-        if (!is_tile_compatible(physical_tile, logical_block)) {
+        if (!is_tile_compatible(physical_tile, logical_block, place_ctx.block_locs[bnum].loc)) {
             VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0,
                       "Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j);
         }
diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp
@@ -436,10 +436,13 @@ bool is_legal_swap_to_location(ClusterBlockId blk, t_pl_loc to) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& place_ctx = g_vpr_ctx.placement();
 
+    auto physical_tile = device_ctx.grid[to.x][to.y].type;
+    auto logical_block = cluster_ctx.clb_nlist.block_type(blk);
+
     if (to.x < 0 || to.x >= int(device_ctx.grid.width())
         || to.y < 0 || to.y >= int(device_ctx.grid.height())
-        || to.z < 0 || to.z >= device_ctx.grid[to.x][to.y].type->capacity
-        || !is_tile_compatible(device_ctx.grid[to.x][to.y].type, cluster_ctx.clb_nlist.block_type(blk))) {
+        || to.z < 0 || to.z >= physical_tile->capacity
+        || !is_tile_compatible(physical_tile, logical_block, to)) {
         return false;
     }
 
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
@@ -838,16 +838,19 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
      * specifies that this is necessary).                                       */
 
     t_clb_opins_used clb_opins_used_locally;
-    int clb_pin, iclass, class_low, class_high;
+    int clb_pin, iclass;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
     clb_opins_used_locally.resize(cluster_ctx.clb_nlist.blocks().size());
 
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         auto type = physical_tile_type(blk_id);
+        auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
 
+        int class_low, class_high;
         get_class_range_for_block(blk_id, &class_low, &class_high);
+
         clb_opins_used_locally[blk_id].resize((int)type->class_inf.size());
 
         if (is_io_type(type)) continue;
@@ -1016,7 +1019,6 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t
     vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source;
 
     int i, j, iclass, inode;
-    int class_low, class_high;
     t_rr_type rr_type;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
@@ -1026,7 +1028,11 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t
 
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         auto type = physical_tile_type(blk_id);
+        auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
+
+        int class_low, class_high;
         get_class_range_for_block(blk_id, &class_low, &class_high);
+
         rr_blk_source[blk_id].resize((int)type->class_inf.size());
         for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) {
             if (iclass >= class_low && iclass <= class_high) {
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
@@ -225,6 +225,7 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr
     std::tie<int, int, int>(pin_index, inst_num, sub_tile_index) = get_pin_index_for_inst(type, pin_index);
 
     t_pin_inst_port pin_inst_port;
+    pin_inst_port.sub_tile_index = sub_tile_index;
     pin_inst_port.capacity_instance = inst_num;
     pin_inst_port.port_index = OPEN;
     pin_inst_port.pin_index_in_port = OPEN;
@@ -732,9 +733,16 @@ void get_class_range_for_block(const ClusterBlockId blk_id,
     auto& place_ctx = g_vpr_ctx.placement();
 
     auto type = physical_tile_type(blk_id);
-    VTR_ASSERT((int)type->class_inf.size() % type->capacity == 0);
-    *class_low = place_ctx.block_locs[blk_id].loc.z * ((int)type->class_inf.size() / type->capacity);
-    *class_high = (place_ctx.block_locs[blk_id].loc.z + 1) * ((int)type->class_inf.size() / type->capacity) - 1;
+    auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
+    int sub_tile_capacity = sub_tile.capacity.total();
+    auto class_range = sub_tile.class_range;
+    int class_range_total = class_range.high - class_range.low + 1;
+
+    VTR_ASSERT((class_range_total) % sub_tile_capacity == 0);
+    int rel_capacity = place_ctx.block_locs[blk_id].loc.z - sub_tile.capacity.low;
+
+    *class_low = rel_capacity * (class_range_total / sub_tile_capacity) + class_range.low;
+    *class_high = (rel_capacity + 1) * (class_range_total / sub_tile_capacity) - 1 + class_range.low;
 }
 
 void get_pin_range_for_block(const ClusterBlockId blk_id,
@@ -744,9 +752,16 @@ void get_pin_range_for_block(const ClusterBlockId blk_id,
     auto& place_ctx = g_vpr_ctx.placement();
 
     auto type = physical_tile_type(blk_id);
-    VTR_ASSERT(type->num_pins % type->capacity == 0);
-    *pin_low = place_ctx.block_locs[blk_id].loc.z * (type->num_pins / type->capacity);
-    *pin_high = (place_ctx.block_locs[blk_id].loc.z + 1) * (type->num_pins / type->capacity) - 1;
+    auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
+    int sub_tile_capacity = sub_tile.capacity.total();
+
+    VTR_ASSERT(sub_tile.num_phy_pins % sub_tile_capacity == 0);
+    int rel_capacity = place_ctx.block_locs[blk_id].loc.z - sub_tile.capacity.low;
+    int rel_pin_low = rel_capacity * (sub_tile.num_phy_pins / sub_tile_capacity);
+    int rel_pin_high = (rel_capacity + 1) * (sub_tile.num_phy_pins / sub_tile_capacity) - 1;
+
+    *pin_low = sub_tile.sub_tile_to_tile_pin_indices[rel_pin_low];
+    *pin_high = sub_tile.sub_tile_to_tile_pin_indices[rel_pin_high];
 }
 
 t_physical_tile_type_ptr find_tile_type_by_name(std::string name, const std::vector<t_physical_tile_type>& types) {
@@ -857,7 +872,7 @@ InstPort parse_inst_port(std::string str) {
         VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find block type named %s", inst_port.instance_name().c_str());
     }
 
-    int num_pins = find_tile_port_by_name(blk_type, inst_port.instance_name().c_str()).num_pins;
+    int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name().c_str()).num_pins;
 
     if (num_pins == OPEN) {
         VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port %s on block type %s", inst_port.port_name().c_str(), inst_port.instance_name().c_str());
@@ -1621,18 +1636,21 @@ static void alloc_and_load_blk_pin_from_port_pin() {
 
     /* Resize and initialize the values to OPEN (-1). */
     int num_types = types.size();
-    f_blk_pin_from_port_pin.resize(device_ctx.physical_tile_types.size());
+    f_blk_pin_from_port_pin.resize(num_types);
     for (int itype = 1; itype < num_types; itype++) {
         int blk_pin_count = 0;
         auto& type = types[itype];
         int num_sub_tiles = type.sub_tiles.size();
         f_blk_pin_from_port_pin[itype].resize(num_sub_tiles);
-        for (int isub_tile; isub_tile < num_sub_tiles; isub_tile++) {
+        for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) {
             int num_ports = type.sub_tiles[isub_tile].ports.size();
             f_blk_pin_from_port_pin[itype][isub_tile].resize(num_ports);
             for (int iport = 0; iport < num_ports; iport++) {
-                f_blk_pin_from_port_pin[itype][isub_tile][iport].push_back(blk_pin_count);
-                blk_pin_count++;
+                int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins;
+                for (int ipin = 0; ipin < num_pins; ipin++) {
+                    f_blk_pin_from_port_pin[itype][isub_tile][iport].push_back(blk_pin_count);
+                    blk_pin_count++;
+                }
             }
         }
     }
@@ -2067,7 +2085,6 @@ void print_switch_usage() {
  * }
  */
 
-// TODO FIX THIS!
 void place_sync_external_block_connections(ClusterBlockId iblk) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& clb_nlist = cluster_ctx.clb_nlist;
@@ -2076,15 +2093,20 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
     auto physical_tile = physical_tile_type(iblk);
     auto logical_block = clb_nlist.block_type(iblk);
 
-    VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0);
-    int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity;
+    int sub_tile_index = get_sub_tile_index(iblk);
+    auto sub_tile = physical_tile->sub_tiles[sub_tile_index];
+
+    VTR_ASSERT(sub_tile.num_phy_pins % sub_tile.capacity.total() == 0);
+
+    int max_num_block_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
+    int physical_pin_offset = get_physical_pin_offset(&sub_tile, physical_tile);
     /* Logical location and physical location is offset by z * max_num_block_pins */
 
     for (auto pin : clb_nlist.block_pins(iblk)) {
         int logical_pin_index = clb_nlist.pin_logical_index(pin);
-        int physical_pin_index = get_physical_pin(physical_tile, logical_block, logical_pin_index);
+        int physical_pin_index = get_physical_pin(sub_tile_index, physical_tile, logical_block, logical_pin_index);
 
-        int new_physical_pin_index = physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins;
+        int new_physical_pin_index = physical_pin_offset + physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins;
 
         auto result = place_ctx.physical_pins.find(pin);
         if (result != place_ctx.physical_pins.end()) {
@@ -2121,6 +2143,18 @@ bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_
     return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end();
 }
 
+bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, t_pl_loc loc) {
+    bool capacity_compatible = false;
+    for (auto& sub_tile : physical_tile->sub_tiles) {
+        if (sub_tile.capacity.is_in_range(loc.z)) {
+            capacity_compatible = true;
+            break;
+        }
+    }
+
+    return capacity_compatible && is_tile_compatible(physical_tile, logical_block);
+}
+
 /**
  * This function returns the most common physical tile type given a logical block
  */
@@ -2215,6 +2249,17 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
     return result->second.pin;
 }
 
+int get_physical_pin_offset(t_sub_tile* sub_tile,
+                            t_physical_tile_type_ptr physical_tile) {
+    int offset = 0;
+
+    for (int isub_tile = 0; isub_tile < sub_tile->index; isub_tile++) {
+        offset += physical_tile->sub_tiles[isub_tile].num_phy_pins;
+    }
+
+    return offset;
+}
+
 int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h
@@ -35,7 +35,9 @@ int get_sub_tile_index(ClusterBlockId blk);
 
 int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node);
 
-void get_class_range_for_block(const ClusterBlockId blk_id, int* class_low, int* class_high);
+void get_class_range_for_block(const ClusterBlockId blk_id,
+                               int* class_low,
+                               int* class_high);
 
 void get_pin_range_for_block(const ClusterBlockId blk_id,
                              int* pin_low,
@@ -146,6 +148,8 @@ int get_max_num_pins(t_logical_block_type_ptr logical_block);
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);
 
+bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, t_pl_loc loc);
+
 //Returns the physical tile type which 'best' matches logical_block
 t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block);
 
@@ -166,6 +170,8 @@ int get_physical_pin(int sub_tile_index,
                      t_physical_tile_type_ptr physical_tile,
                      t_logical_block_type_ptr logical_block,
                      int pin);
+int get_physical_pin_offset(t_sub_tile* sub_tile,
+                            t_physical_tile_type_ptr physical_tile);
 
 //Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index
 int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index);

Original file line number	Diff line number	Diff line change
`@@ -250,7 +250,7 @@ void read_user_pad_loc(const char* pad_loc_file) {`
`250`	`250`
`251`	`251`	`auto physical_tile = device_ctx.grid[i][j].type;`
`252`	`252`	`auto logical_block = cluster_ctx.clb_nlist.block_type(bnum);`
`253`		`- if (!is_tile_compatible(physical_tile, logical_block)) {`
	`253`	`+ if (!is_tile_compatible(physical_tile, logical_block, place_ctx.block_locs[bnum].loc)) {`
`254`	`254`	`VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0,`
`255`	`255`	`"Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j);`
`256`	`256`	`}`