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acomodiacomodi
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vtr_flow: adjust strong golden results
Signed-off-by: Alessandro Comodi <[email protected]>
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‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k4_n4_v7_bidir.xml styr.blif common 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir.xml/styr.blif/common 23568 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1270 0.23 0.00 5.57595 -70.6881 -5.57595 5.57595 0.000181897 0.00014297 0.0196268 0.0159363 16 2004 29 2.43e+06 2.01e+06 -1 -1 0.40 0.07519 0.0633621 1902 24 1378 4371 246547 28194 7.23996 7.23996 -92.3987 -7.23996 0 0 -1 -1 0.05 0.0147415 0.0130549
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k4_n4_v7_longline_bidir.xml styr.blif common 1.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_longline_bidir.xml/styr.blif/common 21548 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1234 0.26 0.00 5.77027 -74.3866 -5.77027 5.77027 0.000190686 0.000150269 0.0199143 0.0162876 18 2361 37 2.43e+06 2.01e+06 -1 -1 0.54 0.0814192 0.0687497 2409 21 1514 4799 386424 43001 8.75717 8.75717 -109.461 -8.75717 0 0 -1 -1 0.06 0.0144257 0.0128624
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k4_n4_v7_l1_bidir.xml styr.blif common 1.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_l1_bidir.xml/styr.blif/common 21528 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1235 0.26 0.00 6.82024 -77.4787 -6.82024 6.82024 0.000179396 0.000141516 0.0197106 0.0159732 10 1513 47 2.43e+06 2.01e+06 -1 -1 0.91 0.0669803 0.0566492 1294 23 1248 4320 389587 82246 8.65232 8.65232 -101.426 -8.65232 0 0 -1 -1 0.10 0.0187415 0.0166916
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k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2808-g534e35fc1 release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1127.18.2.el7.x86_64 x86_64 2020-09-13T17:39:59 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/run002/k4_n4_v7_bidir_pass_gate.xml/styr.blif/common 23280 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1244 0.54 0.00 5.39221 -64.0616 -5.39221 5.39221 0.000181231 0.000144846 0.0215371 0.0174077 16 2062 32 2.43e+06 2.01e+06 -1 -1 1.20 0.113886 0.0960411 2100 30 1484 4823 1048337 136252 11.9977 11.9977 -129.445 -11.9977 0 0 -1 -1 0.13 0.0186144 0.0165004
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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k4_n4_v7_bidir.xml styr.blif common 2.98 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2880-g94605cc4a release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-10-28T12:48:49 acomodi /data/vtr-symbiflow 29392 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1240 0.41 0.00 5.08489 -64.2169 -5.08489 5.08489 0.000386615 0.000328365 0.148014 0.119723 14 2192 35 2.43e+06 2.01e+06 -1 -1 1.78 0.892069 0.796557 2074 28 1367 4077 303850 37423 10.8804 10.8804 -124.692 -10.8804 0 0 -1 -1 0.18 0.101871 0.0883807
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k4_n4_v7_longline_bidir.xml styr.blif common 2.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2880-g94605cc4a release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-10-28T12:48:49 acomodi /data/vtr-symbiflow 29384 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1244 0.50 0.00 6.34208 -76.6011 -6.34208 6.34208 0.000368767 0.000316686 0.15862 0.122338 18 2237 23 2.43e+06 2.01e+06 -1 -1 0.77 0.413346 0.330321 2148 37 1655 4548 331911 32922 8.59204 8.59204 -108.237 -8.59204 0 0 -1 -1 0.36 0.274209 0.253851
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k4_n4_v7_l1_bidir.xml styr.blif common 3.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2880-g94605cc4a release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-10-28T12:48:49 acomodi /data/vtr-symbiflow 28624 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1256 0.43 0.00 6.57291 -77.1404 -6.57291 6.57291 0.000929891 0.000858293 0.138356 0.122628 11 1570 25 2.43e+06 2.01e+06 -1 -1 1.62 0.76144 0.711232 1306 22 1134 3670 276876 51355 8.98996 8.98996 -100.625 -8.98996 0 0 -1 -1 0.28 0.191067 0.133401
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k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-2880-g94605cc4a release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.1 on Linux-4.15.0-101-generic x86_64 2020-10-28T12:48:49 acomodi /data/vtr-symbiflow 29696 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1327 0.71 0.00 5.82995 -68.2589 -5.82995 5.82995 0.000549208 0.000494631 0.117963 0.100719 16 2217 42 2.43e+06 2.01e+06 -1 -1 1.12 0.515908 0.461428 1956 20 1237 4145 763897 90543 13.3321 13.3321 -172.078 -13.3321 0 0 -1 -1 0.18 0.0442731 0.0398836

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