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‎doc/src/vtr/benchmarks.rst

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@@ -38,9 +38,7 @@ They are suitable for FPGA architecture research and medium-scale CAD research.
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stereovision0 Computer Vision
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stereovision1 Computer Vision
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stereovision2 Computer Vision
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stereovision3 Computer Vision
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tpu.32x32.int8 Deep Learning
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tpu.16x16.int8 Deep Learning
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stereovision3 Computer Vision
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================ =================
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The VTR benchmarks are provided as Verilog under: ::
@@ -66,6 +64,51 @@ The Titan benchmarks are suitable for large-scale FPGA CAD research, and FPGA ar
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.. seealso:: :ref:`titan_benchmarks_tutorial`
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Koios Benchmarks
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-----------------
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The Koios benchmarks :cite:`koios_benchmarks` are a set of Deep Learning (DL) benchmarks.
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They are suitable for DL related architecture and CAD research.
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There are 19 designs that include several medium-sized benchmarks and some large benchmarks.
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The designs target different network types (CNNs, RNNs, MLPs, RL) and layer types (fully-connected, convolution, activation, softmax, reduction, eltwise).
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Some of the designs are generated from HLS tools as well.
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These designs use many precisions including binary, different fixed point types int8/16/32, brain floating point (bfloat16), and IEEE half-precision floating point (fp16).
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.. table_koios_benchmarks:
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.. table:: The Koios Benchmarks.
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================= ======================================
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Benchmark Description
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================= ======================================
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clstm_like CLSTM-like accelerator
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dla_like Intel-DLA-like accelerator
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lstm LSTM engine
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tpu_like Google-TPU-v1-like accelerator
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bnn 4-layer binary neural network
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tiny_darknet_like Accelerator for Tiny Darknet
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gemm_layer 20x20 matrix multiplication engine
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attention_layer Transformer self-attention layer
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conv_layer GEMM based convolution
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spmv Sparse matrix vector multiplication
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robot_rl Robot+maze application
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reduction_layer Add/max/min reduction tree
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softmax Softmax classification layer
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conv_layer_hls Sliding window convolution
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eltwise_layer Matrix elementwise add/sub/mult
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================= ======================================
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Koios benchmarks are fully compatible with the full VTR flow. Some Koios benchmarks use advanced DSP features that are available in only a few FPGA architectures provided with VTR. This is because they instantiate DSP macros to implement native FP16 multiplications or use the hard dedicated chains, and these are architecture-specific. If users want to use a different FPGA architecture file, they can replace the macro instantiations in the benchmarks with their equivalents from the FPGA architectures they wish to use.
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Alternatively, users can disable these advanced features. The macro ``complex_dsp`` can be used for this purpose. If complex_dsp is defined in a benchmark file (using ```define complex_dsp`` in the beginning of the benchmark file), then advanced DSP features mentioned above will be used. If a user wants to run a Koios benchmark with FPGA architectures that don't have these advanced DSP features (for example, the flagship architectures: ``$VTR_ROOT/vtr_flow/arch/timing/k6_frac_N10_*_mem32K_40nm*``), then they can remove the line defining the complex_dsp macro. This enables the same functionality with behavioral Verilog that is mapped to the FPGA soft logic when an architecture without the required macro definitions is used.
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The VTR benchmarks are provided as Verilog (enabling full flexibility to modify and change how the designs are implemented) under: ::
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$VTR_ROOT/vtr_flow/benchmarks/verilog/koios
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The FPGA architectures with advanced DSP that work out-of-the-box with Koios benchmarks are available here: ::
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$VTR_ROOT/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.*
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MCNC20 Benchmarks
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-----------------
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The MCNC benchmarks :cite:`mcnc_benchmarks` are a set of small and old (circa 1991) benchmarks.

‎vtr_flow/benchmarks/verilog/tpu.32x32.int8.v renamed to ‎vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v

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//////////////////////////////////////////////////////////////////////////////
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// Author: Aman Arora
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////
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// Logic area (used): 1.72408e+08 MWTAs
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// Resource usage: 5033 LBs, 26 RAMs, 1072 Multipliers
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// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 12500 sec
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// 3. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/k6n10LB_mem20K_complexDSP_customSB_22nm*
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//////////////////////////////////////
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// Parameters
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// Matrix multiplication unit
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////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020-09-27 21:12:45.762386
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// Design Name:
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// Module Name: matmul_32x32_systolic
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module matmul_32x32_systolic(
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clk,
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reset,
@@ -14174,36 +14159,23 @@ wire [2*`DWIDTH-1:0] mul_out_temp;
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reg [2*`DWIDTH-1:0] mul_out_temp_reg;
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always @(posedge clk) begin
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if (reset) begin
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a_flopped <= 0;
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b_flopped <= 0;
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end else begin
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a_flopped <= a;
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b_flopped <= b;
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end
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end
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//assign mul_out = a * b;
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qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp));
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always @(posedge clk) begin
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if (reset) begin
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mul_out_temp_reg <= 0;
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end else begin
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mul_out_temp_reg <= mul_out_temp;
14194-
end
1419514171
end
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//we just truncate the higher bits of the product
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//assign add_out = mul_out + out;
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qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out));
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always @(posedge clk) begin
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if (reset) begin
14203-
out_temp <= 0;
14204-
end else begin
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out_temp <= add_out;
14206-
end
1420714179
end
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//down cast the result
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`ifdef SIMULATION
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reg [7:0] ram[((1<<`AWIDTH)-1):0];
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reg [`DWIDTH-1:0] ram[((1<<`AWIDTH)-1):0];
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reg [31:0] i;
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always @(posedge clk)

‎vtr_flow/benchmarks/verilog/tpu.16x16.int8.v renamed to ‎vtr_flow/benchmarks/verilog/koios/tpu_like.small.v

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//////////////////////////////////////////////////////////////////////////////
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// Author: Aman Arora
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//////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////
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// Logic area (used): 4.95598e+07 MWTAs
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// Resource usage: 1477 LBs, 14 RAMs, 280 Multipliers
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// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3400 sec
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// 3. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/k6n10LB_mem20K_complexDSP_customSB_22nm*
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//////////////////////////////////////
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// Parameters
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// Matrix multiplication unit
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////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020-09-27 21:12:45.762386
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// Design Name:
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// Module Name: matmul_16x16_systolic
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module matmul_16x16_systolic(
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clk,
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reset,
@@ -4448,36 +4433,23 @@ wire [2*`DWIDTH-1:0] mul_out_temp;
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reg [2*`DWIDTH-1:0] mul_out_temp_reg;
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44504435
always @(posedge clk) begin
4451-
if (reset) begin
4452-
a_flopped <= 0;
4453-
b_flopped <= 0;
4454-
end else begin
44554436
a_flopped <= a;
44564437
b_flopped <= b;
4457-
end
44584438
end
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44604440
//assign mul_out = a * b;
44614441
qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp));
44624442

44634443
always @(posedge clk) begin
4464-
if (reset) begin
4465-
mul_out_temp_reg <= 0;
4466-
end else begin
44674444
mul_out_temp_reg <= mul_out_temp;
4468-
end
44694445
end
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44714447
//we just truncate the higher bits of the product
44724448
//assign add_out = mul_out + out;
44734449
qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out));
44744450

44754451
always @(posedge clk) begin
4476-
if (reset) begin
4477-
out_temp <= 0;
4478-
end else begin
44794452
out_temp <= add_out;
4480-
end
44814453
end
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//down cast the result
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49134885
`ifdef SIMULATION
49144886

4915-
reg [7:0] ram[((1<<`AWIDTH)-1):0];
4887+
reg [`DWIDTH-1:0] ram[((1<<`AWIDTH)-1):0];
49164888
reg [31:0] i;
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49184890
always @(posedge clk)

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