Merge remote-tracking branch 'upstream/master' into diagonals

Author: WhiteNinjaZ

.github/scripts/hostsetup.sh

@@ -30,7 +30,6 @@ apt install -y \
   build-essential \
   capnproto \
   clang \
-  cmake \
   ctags \
   curl \
   doxygen \
@@ -65,12 +64,23 @@ apt install -y \
   valgrind \
   zip \
   qt5-default \
+  uuid-dev \
+  default-jdk \
   g++-9 \
   gcc-9 \
   wget
   # Don't include libtbb-dev since it may increase memory usage
   #libtbb-dev \
 
+# installing the latest version of cmake
+apt install -y apt-transport-https ca-certificates gnupg
+wget -qO - https://apt.kitware.com/keys/kitware-archive-latest.asc |apt-key add -
+
+apt-add-repository 'deb https://apt.kitware.com/ubuntu/ bionic main'
+apt update
+apt install -y cmake
+
+
 export PATH="$PATH:/home/kbuilder/.local/bin"
 
 export CC=gcc-9

.github/scripts/install_dependencies.sh

@@ -39,6 +39,8 @@ sudo apt install -y \
   valgrind \
   zip \
   qt5-default \
+  uuid-dev \
+  default-jdk \
   clang-format-7 \
   g++-7 \
   gcc-7 \

.github/workflows/test.yml

@@ -32,8 +32,8 @@ jobs:
           - {test: "vtr_reg_nightly_test4", cores: "16", options: "",          cmake: ""                                             }
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3"                         }
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON"}
-          - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON"                              }
-          - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON"                          }
+          - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON"    }
+          - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON"}
           - {test: "odin_tech_strong",      cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON"                          }
           - {test: "odin_reg_strong",       cores: "16", options: "",          cmake: ""                                             }
 

.gitignore

@@ -12,6 +12,7 @@ bin/
 CMakeCache.txt
 CMakeFiles
 build
+Yosys
 
 #
 #VTR Flow/Tasks
@@ -105,6 +106,11 @@ ODIN_II/usefull_tools/**/track_completed
 #
 Yosys
 
+#
+#ArchFPGA exec dir
+#
+ArchFPGA
+
 #
 #Python
 #

CMakeLists.txt

@@ -55,6 +55,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 # Allow the user to enable building Yosys
 option(WITH_YOSYS "Enable building Yosys" OFF)
 option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
+option(YOSYS_SV_UHDM_PLUGIN "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
 
 set(VTR_VERSION_MAJOR 8)
 set(VTR_VERSION_MINOR 1)
@@ -398,6 +399,14 @@ elseif(${WITH_ODIN})
     endif()
 endif()
 
+# handle cmake params to compile Yosys SystemVerilog/UHDM plugins
+if(${YOSYS_SV_UHDM_PLUGIN})
+    # avoid compiling plugins in case the Yosys frontend is not active
+    if(NOT ${WITH_YOSYS} AND NOT ${ODIN_USE_YOSYS})
+        message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Yosys frontend. Please set either WITH_YOSYS or ODIN_USE_YOSYS on.")
+    endif()
+endif()
+
 #Add extra compilation flags to suppress warnings from some libraries/tools
 # Note that target_compile_options() *appends* to the current compilation options of
 # the specified target

ODIN_II/CMakeLists.txt

@@ -7,8 +7,8 @@ if(ODIN_DEBUG)
     message("*** Compiling with Odin debug flags")
 
     set(ODIN_EXTRA_FLAGS
-        "-g"
-        "-ggdb"
+        "-g3"
+        "-ggdb3"
         "-O0"
         ${ODIN_EXTRA_FLAGS}
     )
@@ -136,6 +136,9 @@ endif()
 if(${ODIN_USE_YOSYS})
     add_definitions("-DODIN_USE_YOSYS=ON")
     add_definitions("-D_YOSYS_")
+    if(${YOSYS_SV_UHDM_PLUGIN})
+        add_definitions("-DYOSYS_SV_UHDM_PLUGIN=ON")
+    endif()
 endif()
 
 add_definitions(-DUSING_BISON -DYYERROR_VERBOSE)

ODIN_II/SRC/BLIFReader.cpp

@@ -348,18 +348,18 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
         /* check for coarse-grain configuration */
         if (configuration.coarsen) {
             if (yosys_subckt_strmap.find(subcircuit_name) != yosys_subckt_strmap.end())
-                new_node->type = yosys_subckt_strmap[subcircuit_name];
+                new_node->type = yosys_subckt_strmap.at(subcircuit_name);
 
             if (new_node->type == NO_OP && yosys_subckt_strmap.find(subcircuit_stripped_name) != yosys_subckt_strmap.end())
-                new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
+                new_node->type = yosys_subckt_strmap.at(subcircuit_stripped_name);
 
             if (new_node->type == NO_OP) {
                 /* in case of weird names, need to add memories manually */
                 int sc_spot = -1;
                 char* yosys_subckt_str = NULL;
                 if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
                     /* specify node type */
-                    new_node->type = yosys_subckt_strmap[yosys_subckt_str];
+                    new_node->type = yosys_subckt_strmap.at(yosys_subckt_str);
                 } else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
                     /* specify node type */
                     new_node->type = HARD_IP;
@@ -387,11 +387,14 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
                                            : operation_list_END;
             }
         } else {
-            new_node->type = odin_subckt_strmap[subcircuit_name];
+            if (odin_subckt_strmap.find(subcircuit_name) != odin_subckt_strmap.end())
+                new_node->type = odin_subckt_strmap.at(subcircuit_name);
 
             /* check for subcircuit prefix prefix */
-            if (subcircuit_stripped_name && new_node->type == NO_OP)
-                new_node->type = odin_subckt_strmap[subcircuit_stripped_name];
+            if (subcircuit_stripped_name
+                && new_node->type == NO_OP
+                && odin_subckt_strmap.find(subcircuit_stripped_name) != odin_subckt_strmap.end())
+                new_node->type = odin_subckt_strmap.at(subcircuit_stripped_name);
 
             if (new_node->type == NO_OP)
                 new_node->type = MEMORY;
@@ -2176,7 +2179,7 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
     char* buffer = NULL;
     attr_t* attributes = new_node->attributes;
     operation_list op = (yosys_subckt_strmap.find(subckt_name) != yosys_subckt_strmap.end())
-                            ? yosys_subckt_strmap[subckt_name]
+                            ? yosys_subckt_strmap.at(subckt_name)
                             : NO_OP;
 
     if (need_params(op)) {

ODIN_II/SRC/GenericReader.cpp

@@ -45,7 +45,8 @@ inline void* GenericReader::_read() {
     void* netlist = NULL;
 
     switch (configuration.input_file_type) {
-        case (file_type_e::_VERILOG): {
+        case (file_type_e::_VERILOG): // fallthrough
+        case (file_type_e::_VERILOG_HEADER): {
             netlist = this->read_verilog();
             break;
         }

ODIN_II/SRC/YYosys.cpp

@@ -51,15 +51,6 @@
 #ifdef ODIN_USE_YOSYS
 #    include "kernel/yosys.h" // Yosys
 USING_YOSYS_NAMESPACE
-#    define YOSYS_ELABORATION_ERROR                        \
-        "\n\tERROR: Yosys failed to perform elaboration, " \
-        "Please look at the log file for the failure cause or pass \'--show_yosys_log\' to Odin-II to see the logs.\n"
-#    define YOSYS_FORK_ERROR \
-        "\n\tERROR: Yosys child process failed to be created\n"
-#else
-#    define YOSYS_INSTALLATION_ERROR                                    \
-        "ERROR: It seems Yosys is not installed in the VTR repository." \
-        " Please compile the VTR with (" ODIN_USE_YOSYS_STR ") flag.\n"
 #endif
 
 /**
@@ -137,11 +128,31 @@ void YYosys::perform_elaboration() {
         /* wait for the Yosys child process */
         auto yosys_status = -1; // the status of the Yosys fork
         waitpid(0, &yosys_status, 0);
-        int yosys_exit_status = WEXITSTATUS(yosys_status);
-
-        if (yosys_exit_status != 0) {
-            error_message(PARSER, unknown_location, "%s", YOSYS_ELABORATION_ERROR);
+        /* check if Yosys exited abnormally */
+        if (!WIFEXITED(yosys_status)) {
+            if (WIFSIGNALED(yosys_status)) {
+                error_message(PARSER, unknown_location,
+                              "Yosys exited with signal %d - %s",
+                              WTERMSIG(yosys_status),
+                              YOSYS_ELABORATION_ERROR);
+            } else if (WIFSTOPPED(yosys_status)) {
+                error_message(PARSER, unknown_location,
+                              "Yosys stopped with signal %d - %s",
+                              WSTOPSIG(yosys_status),
+                              YOSYS_ELABORATION_ERROR);
+            } else {
+                error_message(PARSER, unknown_location, "%s",
+                              "Something strange just happened with Yosys child process.\n");
+            }
+        } else {
+            auto yosys_exit_status = WEXITSTATUS(yosys_status);
+            if (yosys_exit_status != 0)
+                error_message(PARSER, unknown_location,
+                              "Yosys exited with status %d - %s",
+                              yosys_exit_status,
+                              YOSYS_ELABORATION_ERROR);
         }
+
         /* Yosys successfully generated coarse-grain BLIF file */
         this->re_initialize_odin_globals();
     }
@@ -197,6 +208,11 @@ void YYosys::init_yosys() {
     yosys_setup();
     yosys_banner();
 
+#    ifdef YOSYS_SV_UHDM_PLUGIN
+    /* Load SystemVerilog/UHDM plugins in the Yosys frontend */
+    run_pass(std::string("plugin -i systemverilog"));
+#    endif
+
     /* Read VTR baseline library first */
     run_pass(std::string("read_verilog -nomem2reg " + this->vtr_primitives_file));
     run_pass(std::string("setattr -mod -set keep_hierarchy 1 " + std::string(SINGLE_PORT_RAM_string)));
@@ -249,9 +265,34 @@ void YYosys::execute() {
     } else {
         // Read the hardware decription Verilog circuits
         // FOR loop enables include feature for Yosys+Odin (multiple Verilog input files)
-        for (auto verilog_circuit : this->verilog_circuits)
-            run_pass(std::string("read_verilog -sv -nolatches " + verilog_circuit));
-
+        std::string aggregated_circuits;
+        for (auto circuit : this->verilog_circuits)
+            aggregated_circuits += circuit + " ";
+            // Read Verilog/SystemVerilog/UHDM files based on their type, considering the SystemVerilog/UHDM plugins
+#    ifdef YOSYS_SV_UHDM_PLUGIN
+        /* Load SystemVerilog/UHDM plugins in the Yosys frontend */
+        switch (configuration.input_file_type) {
+            case (file_type_e::_VERILOG): // fallthrough
+            case (file_type_e::_VERILOG_HEADER): {
+                run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
+                break;
+            }
+            case (file_type_e::_SYSTEM_VERILOG): {
+                run_pass(std::string("read_systemverilog -debug " + aggregated_circuits));
+                break;
+            }
+            case (file_type_e::_UHDM): {
+                run_pass(std::string("read_uhdm -debug " + aggregated_circuits));
+                break;
+            }
+            default: {
+                error_message(UTIL, unknown_location,
+                              "Invalid file type (%s) for Yosys+Odin-II synthesizer.", file_extension_strmap[configuration.input_file_type]);
+            }
+        }
+#    else
+        run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
+#    endif
         // Check whether cells match libraries and find top module
         if (global_args.top_level_module_name.provenance() == argparse::Provenance::SPECIFIED) {
             run_pass(std::string("hierarchy -check -top " + global_args.top_level_module_name.value() + " -purge_lib"));
@@ -298,7 +339,7 @@ void YYosys::execute() {
         run_pass(std::string("pmuxtree"));
         // To possibly reduce word sizes by Yosys
         run_pass(std::string("wreduce"));
-        // "-undirven" to ensure there is no wire without drive
+        // "-undriven" to ensure there is no wire without drive
         // -noff #potential option to remove all sdffXX and etc. Only dff will remain
         // "opt_muxtree" removes dead branches, "opt_expr" performs const folding and
         // removes "undef" from mux inputs and replace muxes with buffers and inverters

ODIN_II/SRC/adders.cpp

@@ -1064,7 +1064,7 @@ void remove_list_node(t_linked_vptr* pre, t_linked_vptr* next) {
         pre->next = next->next;
     else
         pre->next = NULL;
-    vtr::free(next);
+    delete next;
 }
 
 /*---------------------------------------------------------------------------
@@ -1434,4 +1434,4 @@ nnode_t* check_missing_ports(nnode_t* node, uintptr_t traverse_mark_number, netl
     }
 
     return new_node;
-}
+}

ODIN_II/SRC/enum_str.cpp

@@ -7,11 +7,6 @@ const char* ieee_std_STR[] = {
     "1364-2005",
 };
 
-const char* file_extension_supported_STR[] = {
-    ".v",
-    ".vh",
-};
-
 const char* edge_type_e_STR[] = {
     "UNDEFINED_SENSITIVITY",
     "FALLING_EDGE_SENSITIVITY",
@@ -213,16 +208,28 @@ const char* ids_STR[] = {
     "ids_END"};
 
 /* supported input/output file extensions */
-strmap<file_type_e> file_type_strmap({{"ilang", file_type_e::_ILANG},
-                                      {"verilog", file_type_e::_VERILOG},
-                                      {"verilog_header", file_type_e::_VERILOG_HEADER},
-                                      {"blif", file_type_e::_BLIF},
-                                      {"eblif", file_type_e::_EBLIF},
-                                      {"undef", file_type_e::_UNDEFINED}});
+extern const strbimap<file_type_e> file_extension_strmap({{".ilang", file_type_e::_ILANG},
+                                                          {".v", file_type_e::_VERILOG},
+                                                          {".vh", file_type_e::_VERILOG_HEADER},
+                                                          {".sv", file_type_e::_SYSTEM_VERILOG},
+                                                          {".svh", file_type_e::_SYSTEM_VERILOG_HEADER},
+                                                          {".uhdm", file_type_e::_UHDM},
+                                                          {".blif", file_type_e::_BLIF},
+                                                          {".eblif", file_type_e::_EBLIF}});
+
+/* supported input/output file types */
+extern const strbimap<file_type_e> file_type_strmap({{"ilang", file_type_e::_ILANG},
+                                                     {"verilog", file_type_e::_VERILOG},
+                                                     {"verilog_header", file_type_e::_VERILOG_HEADER},
+                                                     {"systemverilog", file_type_e::_SYSTEM_VERILOG},
+                                                     {"systemverilog_header", file_type_e::_SYSTEM_VERILOG_HEADER},
+                                                     {"uhdm", file_type_e::_UHDM},
+                                                     {"blif", file_type_e::_BLIF},
+                                                     {"eblif", file_type_e::_EBLIF}});
 
 /* available elaborators for Odin-II techmap */
-strmap<elaborator_e> elaborator_strmap({{"odin", elaborator_e::_ODIN},
-                                        {"yosys", elaborator_e::_YOSYS}});
+extern const strmap<elaborator_e> elaborator_strmap({{"odin", elaborator_e::_ODIN},
+                                                     {"yosys", elaborator_e::_YOSYS}});
 
 /**
  * global hashmap of odin subckt types
@@ -232,10 +239,10 @@ strmap<elaborator_e> elaborator_strmap({{"odin", elaborator_e::_ODIN},
  *  FIRST_ELEMENT: model name showing in a blif file
  *  SECOND_ELEMENT: corresponding Odin-II cell type
  */
-strmap<operation_list> odin_subckt_strmap({{"multiply", MULTIPLY},
-                                           {"mult_", MULTIPLY},
-                                           {"adder", ADD},
-                                           {"sub", MINUS}});
+extern const strmap<operation_list> odin_subckt_strmap({{"multiply", MULTIPLY},
+                                                        {"mult_", MULTIPLY},
+                                                        {"adder", ADD},
+                                                        {"sub", MINUS}});
 
 /**
  * global hashmap of yosys subckt types
@@ -254,7 +261,7 @@ strmap<operation_list> odin_subckt_strmap({{"multiply", MULTIPLY},
  * in the BLIF Elaboration phase to make the new node compatible
  * with the Odin-II partial mapper.
  */
-strmap<operation_list> yosys_subckt_strmap({
+extern const strmap<operation_list> yosys_subckt_strmap({
     {"$_ANDNOT_", operation_list_END},
     {"$_AND_", operation_list_END},          // (A, B, Y)
     {"$_AOI3_", operation_list_END},         // (A, B, C, Y)

ODIN_II/SRC/include/GenericIO.hpp

@@ -50,7 +50,7 @@ class GenericIO {
     virtual void _write(const netlist_t* netlist);
 
     /* to create the output file */
-    virtual void _create_file(const char* file_name, const file_type_e file_type = _UNDEFINED);
+    virtual void _create_file(const char* file_name, const file_type_e file_type = file_type_e_END);
 };
 
 #endif // __GENERIC_IO_H__

ODIN_II/SRC/include/GenericWriter.hpp

@@ -62,7 +62,7 @@ class GenericWriter : public GenericIO {
      */
 
     /* to create the output file */
-    void _create_file(const char* file_name, const file_type_e file_type = _UNDEFINED);
+    void _create_file(const char* file_name, const file_type_e file_type = file_type_e_END);
 
   protected:
     FILE* output_file;