Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into pack_pattern_root_block

Author: amin1377

.github/workflows/stale.yml

@@ -10,6 +10,11 @@ jobs:
     steps:
       - uses: actions/stale@v9
         with:
+          # Set default number of days before being marked stale to 100 years
+          # This will be overriden by "days-before-issue-stale" and "days-before-pr-stale"
+          # This is done to avoid marking PRs as stale, as it is not something
+          # we want to do.
+          days-before-stale: 36500
           # The message to be shown for stale issues
           stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
           close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'

doc/src/vpr/command_line_usage.rst

@@ -1730,6 +1730,16 @@ Analysis Options
 
     **Default:** ``unconnected``
 
+.. option:: --post_synth_netlist_module_parameters { on | off }
+
+    Controls whether the post-synthesis netlist output by VTR can use Verilog parameters
+    or not. When using the post-synthesis netlist for external timing analysis,
+    some tools cannot accept the netlist if it contains parameters. By setting
+    this option to ``off``, VPR will try to represent the netlist using non-parameterized
+    modules.
+
+    **Default:** ``on``
+
 .. option:: --timing_report_npaths <int>
 
     Controls how many timing paths are reported.

libs/libarchfpga/src/arch_check.cpp

@@ -26,7 +26,7 @@ extern "C" {
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-bool check_model_clocks(t_model* model, const char* file, uint32_t line);
+bool check_model_clocks(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks the correctness of the combinational sinks in the model inputs to outputs connections
@@ -35,7 +35,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line);
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line);
+bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks whether the I/O ports can have timing specifications based on their connectivity.
@@ -47,7 +47,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line);
+void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks the consistency of the mappings between a logical block and the corresponding physical tile.

libs/libarchfpga/src/arch_check.h

@@ -18,18 +18,9 @@
 /* Value for UNDEFINED data */
 constexpr int UNDEFINED = -1;
 
-/** The total number of predefined blif models */
-constexpr int NUM_MODELS_IN_LIBRARY = 4;
-
 /* Maximum value for minimum channel width to avoid overflows of short data type.               */
 constexpr int MAX_CHANNEL_WIDTH = 8000;
 
-/* Built-in library models */
-constexpr const char* MODEL_NAMES = ".names";
-constexpr const char* MODEL_LATCH = ".latch";
-constexpr const char* MODEL_INPUT = ".input";
-constexpr const char* MODEL_OUTPUT = ".output";
-
 enum class e_arch_format {
     VTR,            ///<VTR-specific device XML format
     FPGAInterchange ///<FPGA Interchange device format