Removing an old matmul benchmark. A modified version of this benchmark is now in the Koios benchmarks (named gemm_layer.v).

Also, removing the synthesis results for 3 benchmarks (tpu.16x16, tpu.32x32 and matmul_8x8_fp16) from ODIN-II synthesis regression golden results.
These benchmarks are no longer present in the vtr_flow/benchmarks/verilog directory. They are not in the Koios suite under different names.

Author: aman26kbm

ODIN_II/regression_test/benchmark/task/large/synthesis_result.json

@@ -1161,89 +1161,6 @@
         "Longest Path": 2,
         "Average Path": 2
     },
-    "large/tpu.16x16.int8/k6_frac_N10_frac_chain_mem32K_40nm": {
-        "test_name": "large/tpu.16x16.int8/k6_frac_N10_frac_chain_mem32K_40nm",
-        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
-        "verilog": "tpu.16x16.int8.v",
-        "warnings": [
-            "tpu.16x16.int8.v:2298:7 [AST] Odin does not handle signed REG (counter)"
-        ],
-        "max_rss(MiB)": 241.4,
-        "exec_time(ms)": 2140.9,
-        "synthesis_time(ms)": 2135.1,
-        "Latch Drivers": 1,
-        "Pi": 354,
-        "Po": 289,
-        "logic element": 59049,
-        "latch": 22362,
-        "Adder": 4988,
-        "Multiplier": 288,
-        "Memory": 256,
-        "generic logic size": 4,
-        "Longest Path": 1596,
-        "Average Path": 4,
-        "Estimated LUTs": 70497,
-        "Total Node": 86944
-    },
-    "large/tpu.32x32.int8/k6_frac_N10_frac_chain_mem32K_40nm": {
-        "test_name": "large/tpu.32x32.int8/k6_frac_N10_frac_chain_mem32K_40nm",
-        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
-        "verilog": "tpu.32x32.int8.v",
-        "warnings": [
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[0] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[1] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[2] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[3] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[4] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[5] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[6] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:1569:18 [NETLIST] This module port u_systolic_data_setup.final_mat_mul_size[7] is unused in module systolic_data_setup",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[0] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[1] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[2] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[3] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[4] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[5] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[6] is unused in module output_logic",
-            "tpu.32x32.int8.v:2881:18 [NETLIST] This module port u_output_logic.final_mat_mul_size[7] is unused in module output_logic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[0] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[1] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[2] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[3] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[4] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[5] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[6] is unused in module matmul_32x32_systolic",
-            "tpu.32x32.int8.v:15361:1 [NETLIST] This module port u_matmul.final_mat_mul_size[7] is unused in module matmul_32x32_systolic"
-        ],
-        "max_rss(MiB)": 811.1,
-        "exec_time(ms)": 8389.9,
-        "synthesis_time(ms)": 8384.1,
-        "Latch Drivers": 1,
-        "Pi": 642,
-        "Po": 545,
-        "logic element": 190121,
-        "latch": 85146,
-        "Adder": 18297,
-        "Multiplier": 1088,
-        "Memory": 512,
-        "generic logic size": 4,
-        "Longest Path": 3164,
-        "Average Path": 4,
-        "Estimated LUTs": 209209,
-        "Total Node": 295165
-    },
-    "large/matmul_8x8_fp16/k6_frac_N10_frac_chain_mem32K_40nm": {
-        "test_name": "large/matmul_8x8_fp16/k6_frac_N10_frac_chain_mem32K_40nm",
-        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
-        "verilog": "matmul_8x8_fp16.v",
-        "exit": 134,
-        "errors": [
-            "matmul_8x8_fp16.v:1648:1 [AST] Can't find module name mac_fp"
-        ],
-        "warnings": [
-            "matmul_8x8_fp16.v:1212:7 [AST] Odin does not handle signed REG (counter)"
-        ]
-    },
     "DEFAULT": {
         "test_name": "n/a",
         "architecture": "n/a",