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‎.github/workflows/test.yml

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -155,17 +155,17 @@ jobs:
155155
include: [
156156
{
157157
name: 'Basic',
158-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
158+
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON',
159159
suite: 'vtr_reg_basic'
160160
},
161161
{
162162
name: 'Basic with NO_GRAPHICS',
163-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
163+
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off -DODIN_USE_YOSYS=ON',
164164
suite: 'vtr_reg_basic'
165165
},
166166
{
167167
name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
168-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
168+
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on -DODIN_USE_YOSYS=ON',
169169
suite: 'vtr_reg_basic'
170170
},
171171
{
@@ -238,7 +238,7 @@ jobs:
238238

239239
- name: Test
240240
env:
241-
CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on'
241+
CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON'
242242
BUILD_TYPE: debug
243243
LSAN_OPTIONS: 'exitcode=42' #Use a non-standard exit code to ensure LSAN errors are detected
244244
run: |

‎.gitignore

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,11 @@ ODIN_II/usefull_tools/**/track_completed
100100
*.o
101101
*.a
102102

103+
#
104+
#Yosys exec dir
105+
#
106+
Yosys
107+
103108
#
104109
#Python
105110
#

‎ODIN_II/SRC/BLIFReader.cpp

Lines changed: 25 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -336,10 +336,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
336336
t_model* hb_model = NULL;
337337
nnode_t* new_node = allocate_nnode(my_location);
338338

339-
// Name the node subcircuit_name~hard_block_number so that the name is unique.
340339
static long hard_block_number = 0;
341-
odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
342-
new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
343340

344341
// init the edge sensitivity of hard block
345342
if (configuration.coarsen)
@@ -357,21 +354,15 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
357354
new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
358355

359356
if (new_node->type == NO_OP) {
360-
char new_name[READ_BLIF_BUFFER];
361-
vtr::free(new_node->name);
362357
/* in case of weird names, need to add memories manually */
363358
int sc_spot = -1;
364359
char* yosys_subckt_str = NULL;
365360
if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
366361
/* specify node type */
367362
new_node->type = yosys_subckt_strmap[yosys_subckt_str];
368-
/* specify node name */
369-
odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
370363
} else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
371364
/* specify node type */
372365
new_node->type = HARD_IP;
373-
/* specify node name */
374-
odin_sprintf(new_name, "\\%s~%ld", subcircuit_stripped_name, hard_block_number - 1);
375366
/* Detect used hard block for the blif generation */
376367
hb_model = find_hard_block(subcircuit_stripped_name);
377368
if (hb_model) {
@@ -381,7 +372,6 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
381372
error_message(PARSE_BLIF, unknown_location,
382373
"Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
383374
}
384-
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
385375

386376
// CLEAN UP
387377
vtr::free(yosys_subckt_str);
@@ -493,6 +483,31 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
493483
output_nets_hash->add(name, new_net);
494484
}
495485

486+
if (!configuration.coarsen
487+
|| !configuration.decode_names
488+
|| new_node->type == SPRAM
489+
|| new_node->type == DPRAM) {
490+
// Name the node subcircuit_name~hard_block_number so that the name is unique.
491+
odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
492+
new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
493+
} else {
494+
// Find the basename of the output pin and name the node
495+
// with BASENAME^TYPE
496+
char* splitter = strrchr(new_node->output_pins[0]->net->name, '.');
497+
char* output_pin_fullname = new_node->output_pins[0]->net->name;
498+
499+
// there is only a top module, no instantiation of submodules
500+
if (splitter == NULL)
501+
splitter = strchr(output_pin_fullname, '^');
502+
503+
char basename[READ_BLIF_BUFFER];
504+
size_t basename_len = splitter - output_pin_fullname;
505+
506+
strncpy(basename, output_pin_fullname, basename_len);
507+
basename[basename_len] = '\0';
508+
new_node->name = node_name(new_node, basename);
509+
}
510+
496511
// Create a fake ast node.
497512
if (!configuration.coarsen || new_node->type == HARD_IP) {
498513
new_node->related_ast_node = create_node_w_type(HARD_BLOCK, my_location);

‎ODIN_II/SRC/enum_str.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,14 +42,14 @@ const char* LUTRAM_string = "lutram_ram";
4242

4343
const char* operation_list_STR[][2] = {
4444
{"NO_OP", "nOP"},
45+
{"CLOCK_NODE", "CLK"},
46+
{"INPUT_NODE", "IN"},
47+
{"OUTPUT_NODE", "OUT"},
4548
{"MULTI_PORT_MUX", "nMUX"}, // port 1 = control, port 2+ = mux options
4649
{"FF_NODE", "FF"},
4750
{"BUF_NODE", "BUF"},
48-
{"INPUT_NODE", "IN"},
49-
{"OUTPUT_NODE", "OUT"},
5051
{"GND_NODE", "GND"},
5152
{"VCC_NODE", "VCC"},
52-
{"CLOCK_NODE", "CLK"},
5353
{"ADD", "ADD"}, // +
5454
{"MINUS", "MIN"}, // -
5555
{"BITWISE_NOT", "bNOT"}, // ~

‎ODIN_II/SRC/include/config_t.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ struct config_t {
1717
bool fflegalize; // Legalize DFFs by making them rising edge
1818
bool coarsen; // Specify if the input BLIF is coarse-grain
1919
bool show_yosys_log; // Print Yosys logs into the standard output stream
20+
bool decode_names; // Extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming
2021

2122
bool output_ast_graphs; // switch that outputs ast graphs per node for use with GRaphViz tools
2223
bool output_netlist_graphs; // switch that outputs netlist graphs per node for use with GraphViz tools

‎ODIN_II/SRC/include/odin_types.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@ struct global_args_t {
113113
argparse::ArgValue<bool> fflegalize; // makes flip-flops rising edge sensitive
114114
argparse::ArgValue<bool> coarsen; // tells Odin-II that the input blif is coarse-grain
115115
argparse::ArgValue<bool> show_yosys_log; // Show Yosys output logs into the standard output stream
116+
argparse::ArgValue<bool> decode_names; // Extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming
116117

117118
argparse::ArgValue<std::string> adder_def; //DEPRECATED
118119

@@ -240,14 +241,14 @@ enum init_value_e {
240241
*/
241242
enum operation_list {
242243
NO_OP,
244+
CLOCK_NODE,
245+
INPUT_NODE,
246+
OUTPUT_NODE,
243247
MULTI_PORT_MUX, // port 1 = control, port 2+ = mux options
244248
FF_NODE,
245249
BUF_NODE,
246-
INPUT_NODE,
247-
OUTPUT_NODE,
248250
GND_NODE,
249251
VCC_NODE,
250-
CLOCK_NODE,
251252
ADD, // +
252253
MINUS, // -
253254
BITWISE_NOT, // ~

‎ODIN_II/SRC/netlist_statistic.cpp

Lines changed: 32 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -478,14 +478,39 @@ void compute_statistics(netlist_t* netlist, bool display) {
478478
get_upward_stat(&netlist->output_node_stat, netlist->top_output_nodes, netlist->num_top_output_nodes, netlist, travelsal_id + 1);
479479

480480
if (display) {
481+
std::string hdr = "";
481482
printf("\n\t==== Stats ====\n");
482-
for (long long op = 0; op < operation_list_END; op += 1) {
483-
if (netlist->num_of_type[op] > UNUSED_NODE_TYPE) {
484-
std::string hdr = std::string("Number of <")
485-
+ operation_list_STR[op][ODIN_LONG_STRING]
486-
+ "> node: ";
487-
488-
printf("%-42s%lld\n", hdr.c_str(), netlist->num_of_type[op]);
483+
for (auto op = 0; op < operation_list_END; op += 1) {
484+
switch (op) {
485+
// For top IO nodes generate detailed info since the design might have unconnected input nodes
486+
case INPUT_NODE: {
487+
auto unused_pi = netlist->num_top_input_nodes - netlist->num_of_type[op] - netlist->num_of_type[CLOCK_NODE];
488+
if (unused_pi > 0) {
489+
hdr = std::string("Number of unused <")
490+
+ operation_list_STR[op][ODIN_LONG_STRING]
491+
+ "> node: ";
492+
printf("%-42s%lld\n", hdr.c_str(), unused_pi);
493+
}
494+
[[fallthrough]];
495+
}
496+
case OUTPUT_NODE: {
497+
auto unused_po = netlist->num_top_output_nodes - netlist->num_of_type[op];
498+
if (unused_po > 0) {
499+
hdr = std::string("Number of unused <")
500+
+ operation_list_STR[op][ODIN_LONG_STRING]
501+
+ "> node: ";
502+
printf("%-42s%lld\n", hdr.c_str(), unused_po);
503+
}
504+
[[fallthrough]];
505+
}
506+
default: {
507+
if (netlist->num_of_type[op] > UNUSED_NODE_TYPE) {
508+
hdr = std::string("Number of <")
509+
+ operation_list_STR[op][ODIN_LONG_STRING]
510+
+ "> node: ";
511+
printf("%-42s%lld\n", hdr.c_str(), netlist->num_of_type[op]);
512+
}
513+
}
489514
}
490515
}
491516
printf("%-42s%lld\n", "Total estimated number of lut: ", netlist->num_logic_element);

‎ODIN_II/SRC/odin_ii.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -533,6 +533,12 @@ void get_options(int argc, char** argv) {
533533
.help("TCL file")
534534
.metavar("TCL_FILE");
535535

536+
ext_elaborator_group.add_argument(global_args.decode_names, "--decode_names")
537+
.help("Enable extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming")
538+
.default_value("false")
539+
.action(argparse::Action::STORE_TRUE)
540+
.metavar("DECODE_NAMES");
541+
536542
auto& other_grp = parser.add_argument_group("other options");
537543

538544
other_grp.add_argument(global_args.show_help, "-h")
@@ -752,6 +758,10 @@ void get_options(int argc, char** argv) {
752758
configuration.elaborator_type = elaborator_e::_YOSYS;
753759
}
754760

761+
if (global_args.decode_names.provenance() == argparse::Provenance::SPECIFIED) {
762+
configuration.decode_names = global_args.decode_names;
763+
}
764+
755765
if (global_args.write_netlist_as_dot.provenance() == argparse::Provenance::SPECIFIED) {
756766
configuration.output_netlist_graphs = global_args.write_netlist_as_dot;
757767
}
@@ -809,6 +819,7 @@ void set_default_config() {
809819
configuration.coarsen = false;
810820
configuration.fflegalize = false;
811821
configuration.show_yosys_log = false;
822+
configuration.decode_names = false;
812823
configuration.tcl_file = "";
813824
configuration.output_file_type = file_type_e::_BLIF;
814825
configuration.elaborator_type = elaborator_e::_ODIN;

‎doc/src/vtr/tasks.rst

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -144,15 +144,17 @@ Optional Fields
144144

145145
Absolute path or relative to ``$VTR_ROOT/vtr_flow/``.
146146

147-
Note: Multiple _includes_dir_ are NOT allowed in a task config file.
147+
Note: Multiple `includes_dir` are NOT allowed in a task config file.
148148

149-
* **include_list_add**: A path to an _include_ file, which is relative to _includes_dir_
149+
* **include_list_add**: A path to an `include` file, which is relative to `includes_dir`
150150

151-
Multiple _include_list_add_ can be provided.
151+
Multiple `include_list_add` can be provided.
152152

153-
_include_ files could act as the top module complementary, like definitions, macros or sub-modules.
153+
`include` files could act as the top module complementary, like definitions, memory initialization files, macros or sub-modules.
154+
155+
Note: Only `include` files, written in supported HDLs by each frontend, are synthesized. The others are only copied to the destination folder.
154156

155-
Note: _include_ files will be shared among all benchmark circuits in the task config file.
157+
Note: `include` files will be shared among all benchmark circuits in the task config file.
156158

157159
* **pass_requirements_file**: :ref:`vtr_pass_requirements` file.
158160

‎doc/src/yosys+odin/user_guide.rst

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@ Synthesis Arguments
2626
**`--elaborator`** **[odin (default), yosys]** **Specify the tool that should perform the HDL elaboration**
2727
**`--fflegalize`** **Converts latches' sensitivity to the rising edge as required by VPR**
2828
**`--show_yosys_log`** **Showing the Yosys elaboration logs in the console window**
29+
**`--decode_names`** **Enable extracting hierarchical information from Yosys coarse-grained BLIF file for signal naming \
30+
(the VTR flow scripts take advantage of this option by default)**
2931
======================= ============================== =================================================================================================
3032

3133

@@ -42,6 +44,15 @@ Passes a Verilog file to Yosys for performing elaboration.
4244
The BLIF elaboration and partial mapping phases will be executed on the generated netlist.
4345
However, all latches in the Yosys+Odin-II output file will be rising edge.
4446

47+
.. code-block:: bash
48+
49+
./odin_II --elaborator yosys -V <Path/to/Verilog/file> --decode_names
50+
51+
52+
Performs the design elaboration by Yosys parsers and generates a coarse-grained netlist in BLIF.
53+
Odin-II then extracts the hierarchical information of subcircuits to use for signal naming when reading the coarse-grained BLIF file.
54+
The BLIF elaboration and partial mapping phases will be executed on the generated netlist.
55+
4556
.. code-block:: bash
4657
4758
./odin_II -b <Path/to/BLIF/file> --coarsen --fflegalize

‎doc/src/yosys/dev_guide.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ How to add new changes?
3232
-----------------------
3333

3434
The Yosys synthesis commands, including the generic synthesis and additional VTR specific configurations, are provided
35-
in `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_
36-
script is perhaps the first file developers may require to change.
35+
in `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_
36+
script is perhaps the first file developers may be required to change.
3737

3838
Moreover, the `yosys_models.v <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/yosys_models.v>`_ file includes the required definitions for Yosys to how it should infer implicit
3939
memories and instantiate arithmetic operations, such as addition, subtraction, and multiplication. Therefore, to alter these

‎doc/src/yosys/structure.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ Structure of Yosys Synthesis Files and the Yosys External Library Library
1818
│ ├── multiply.v
1919
│ ├── single_port_ram.v
2020
│ ├── spram_rename.v
21-
│ ├── synthesis.ys
21+
│ ├── synthesis.tcl
2222
│ └── yosys_models.v
2323
└── libs
2424
└── EXTERNAL

‎libs/EXTERNAL/CMakeLists.txt

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,20 @@ endif()
1818
# Yosys is compiled only if the user ask for it
1919
if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
2020
add_subdirectory(libyosys)
21+
22+
# In addition to libyosys in the build folder, we copy the libyosys directory
23+
# into a temporary folder in the VTR root, named Yosys, to have access to Yosys
24+
# execs for using in VTR scripts (similar to VPR/vpr or ODIN_II/odin_II)
25+
add_custom_target(vtr-yosys ALL
26+
DEPENDS yosys
27+
COMMAND ${CMAKE_COMMAND} -E
28+
remove_directory ${VTR_SOURCE_DIR}/Yosys/
29+
COMMAND ${CMAKE_COMMAND} -E
30+
make_directory ${VTR_SOURCE_DIR}/Yosys/
31+
COMMAND ${CMAKE_COMMAND} -E
32+
copy_directory ${CMAKE_CURRENT_BINARY_DIR}/libyosys ${VTR_SOURCE_DIR}/Yosys/
33+
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
34+
2135
endif()
2236

2337
if(${VTR_ENABLE_CAPNPROTO})

‎libs/EXTERNAL/libyosys/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ add_dependencies(libyosys yosys)
4444
# specify where the library is and where to find the headers
4545
set_target_properties(libyosys
4646
PROPERTIES PREFIX "" #Avoid extra 'lib' prefix
47-
IMPORTED_LOCATION ${LIB_FILE}
47+
IMPORTED_LOCATION ${BINARY_LIB_FILE}
4848
INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS})
4949

5050

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