[test] update strong odin golden

amin1377 · amin1377 · commit 5ecd36fb7692 · 2024-08-26T18:40:05.000-04:00
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.13	vpr	202.88 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207748	1	4	28	32	2	10	9	4	4	16	clb	auto	51.9 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583271	0.000535066	0.00308541	0.00258587	8	12	5	72000	72000	5593.62	349.601	0.86	0.0614891	0.0547303	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.010886	0.00952369	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.18	vpr	203.46 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208344	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.14	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000579833	0.000533235	0.00309464	0.0025854	8	12	5	72000	72000	5593.62	349.601	0.86	0.0608434	0.0541405	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108096	0.00946964	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.13	vpr	202.64 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207504	1	4	28	32	2	10	9	4	4	16	clb	auto	51.4 MiB	0.14	20	27	15	8	4	193.1 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000572304	0.000525073	0.00310109	0.00259353	8	12	5	72000	72000	5593.62	349.601	0.86	0.0611009	0.054383	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108444	0.00950833	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.34	vpr	203.48 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208364	1	4	28	32	2	10	9	4	4	16	clb	auto	51.8 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000590751	0.000540821	0.00316208	0.00264441	8	12	5	72000	72000	5593.62	349.601	0.90	0.0650926	0.0576217	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0118781	0.0104259	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.30	vpr	203.96 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208860	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.53	0.000590039	0.000540401	0.00316168	0.00264575	8	12	5	72000	72000	5593.62	349.601	0.91	0.0661082	0.058795	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.011084	0.00968987	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.36	vpr	202.70 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207564	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.15	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000584676	0.000538033	0.00319424	0.00261523	8	12	5	72000	72000	5593.62	349.601	0.91	0.0673054	0.0593848	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.18	-1	-1	0.01	0.0112706	0.00986656	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	202.38 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207240	2	2	22	24	2	4	6	4	4	16	clb	auto	51.8 MiB	0.10	4	15	2	10	3	193.1 MiB	0.02	0.00	1.297	0	0	1.297	0.50	0.000500888	0.000459494	0.00266891	0.00218049	4	6	2	72000	36000	2827.54	176.721	0.84	0.0129763	0.0108607	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00609768	0.00517486	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	201.04 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	205860	2	2	22	24	2	4	6	4	4	16	clb	auto	51.6 MiB	0.11	4	15	2	10	3	193.0 MiB	0.02	0.00	1.297	0	0	1.297	0.53	0.000520067	0.000476752	0.00285601	0.00232812	4	6	2	72000	36000	2827.54	176.721	0.63	0.0112241	0.0092358	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.03	0.17	-1	-1	0.01	0.00632552	0.00538297	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt

Original file line number	Diff line number	Diff line change
`@@ -1,2 +1,2 @@`
`1`	`1`	arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
`2`		-timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 3.91 vpr 202.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 84e0337-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:44:22 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 207240 2 2 22 24 2 4 6 4 4 16 clb auto 51.8 MiB 0.10 4 15 2 10 3 193.1 MiB 0.02 0.00 1.297 0 0 1.297 0.50 0.000500888 0.000459494 0.00266891 0.00218049 4 6 2 72000 36000 2827.54 176.721 0.84 0.0129763 0.0108607 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00609768 0.00517486
	`2`	+timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 3.91 vpr 201.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 884dcc8-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-25T20:48:27 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 205860 2 2 22 24 2 4 6 4 4 16 clb auto 51.6 MiB 0.11 4 15 2 10 3 193.0 MiB 0.02 0.00 1.297 0 0 1.297 0.53 0.000520067 0.000476752 0.00285601 0.00232812 4 6 2 72000 36000 2827.54 176.721 0.63 0.0112241 0.0092358 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.03 0.17 -1 -1 0.01 0.00632552 0.00538297