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Merge branch 'master' into Yosys42
2 parents 06a9608 + 31f60a5 commit 5ebe2df

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‎.github/workflows/test.yml

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@@ -64,27 +64,9 @@ jobs:
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- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
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- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
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- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
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<<<<<<< HEAD
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#- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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#- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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=======
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<<<<<<< HEAD
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- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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=======
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<<<<<<< HEAD
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#- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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#- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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=======
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#- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=OFF", extra_pkgs: ""}
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>>>>>>> a23006e1e (vtr golden result updated)
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>>>>>>> f839aab8a (vtr golden result updated)
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>>>>>>> 53f47802d (Re-commit changes after soft reset)
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env:
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DEBIAN_FRONTEND: "noninteractive"

‎vpr/src/base/ShowSetup.cpp

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@@ -608,7 +608,7 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts,
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}
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static void ShowNetlistOpts(const t_netlist_opts& NetlistOpts) {
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VTR_LOG("NetlistOpts.abosrb_buffer_luts : %s\n", (NetlistOpts.absorb_buffer_luts) ? "true" : "false");
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VTR_LOG("NetlistOpts.absorb_buffer_luts : %s\n", (NetlistOpts.absorb_buffer_luts) ? "true" : "false");
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VTR_LOG("NetlistOpts.sweep_dangling_primary_ios : %s\n", (NetlistOpts.sweep_dangling_primary_ios) ? "true" : "false");
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VTR_LOG("NetlistOpts.sweep_dangling_nets : %s\n", (NetlistOpts.sweep_dangling_nets) ? "true" : "false");
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VTR_LOG("NetlistOpts.sweep_dangling_blocks : %s\n", (NetlistOpts.sweep_dangling_blocks) ? "true" : "false");

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt

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@@ -7,3 +7,4 @@ k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 61.77 MiB -1 -1 0.07 20064
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k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.56 vpr 61.92 MiB -1 -1 0.07 20368 1 0.02 -1 -1 32848 -1 -1 0 1 0 0 success v8.0.0-10480-gb00638420 release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-07-09T01:24:04 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing 63408 1 1 1 2 0 1 2 3 3 9 -1 auto 23.4 MiB 0.00 2 3 1 2 0 61.9 MiB 0.00 0.00 0.205011 -0.205011 -0.205011 nan 0.00 1.4641e-05 4.774e-06 8.4923e-05 3.0381e-05 2 1 1 53894 0 1165.58 129.509 0.00 0.000171005 6.9037e-05 254 297 -1 1 1 1 1 17 8 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 6.259e-05 2.907e-05
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k6_N10_mem32K_40nm.xml single_ff.v common 0.55 vpr 61.64 MiB -1 -1 0.07 20368 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-10480-gb00638420 release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-07-09T01:24:04 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing 63124 2 1 3 4 1 3 4 3 3 9 -1 auto 23.3 MiB 0.00 4 9 6 0 3 61.6 MiB 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 0.00 1.9055e-05 1.0869e-05 8.77e-05 4.7964e-05 2 4 2 53894 53894 1165.58 129.509 0.00 0.000214022 0.000117563 254 297 -1 4 2 3 3 75 50 0.577715 0.577715 -1.12352 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000111083 6.647e-05
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k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.69 vpr 61.65 MiB -1 -1 0.07 20672 1 0.04 -1 -1 33092 -1 -1 1 2 0 0 success v8.0.0-10480-gb00638420 release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-07-09T01:24:04 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing 63132 2 1 3 4 1 3 4 3 3 9 -1 auto 23.4 MiB 0.00 4 9 6 0 3 61.7 MiB 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 0.00 1.8761e-05 8.417e-06 9.6466e-05 5.2411e-05 2 4 2 53894 53894 1165.58 129.509 0.00 0.000233534 0.000132023 254 297 -1 4 2 3 3 75 50 0.577715 0.577715 -1.12352 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000221939 0.000107927
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‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 6.22 vpr 63.81 MiB -1 -1 0.18 21888 14 0.26 -1 -1 36868 -1 -1 27 32 0 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 65344 32 32 277 309 1 204 91 17 17 289 -1 unnamed_device 25.3 MiB 0.39 1387 6619 1257 4855 507 63.8 MiB 0.04 0.00 6.6399 -138.036 -6.6399 6.6399 0.68 0.000188205 0.000152593 0.00975451 0.0080884 36 3404 21 6.55708e+06 325485 612192. 2118.31 3.00 0.0706458 0.0587011 22750 144809 -1 2974 16 1393 4308 256375 56680 7.0397 7.0397 -159.412 -7.0397 0 0 782063. 2706.10 0.28 0.05 0.09 -1 -1 0.28 0.0139673 0.0126438 183 182 -1 -1 -1 -1
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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 6.27 vpr 63.86 MiB -1 -1 0.19 21888 14 0.28 -1 -1 36548 -1 -1 31 30 0 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 65396 30 32 272 304 1 210 93 17 17 289 -1 unnamed_device 25.3 MiB 0.47 1276 5973 1192 4287 494 63.9 MiB 0.04 0.00 6.36996 -127.262 -6.36996 6.36996 0.67 0.000203108 0.000167027 0.00873092 0.00739044 34 3277 49 6.55708e+06 373705 585099. 2024.56 3.03 0.103849 0.0874778 22462 138074 -1 2875 17 1416 4137 223934 52885 6.97296 6.97296 -149.692 -6.97296 0 0 742403. 2568.87 0.26 0.05 0.08 -1 -1 0.26 0.015258 0.0137757 184 181 -1 -1 -1 -1
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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 9.33 vpr 63.73 MiB -1 -1 0.17 21432 11 0.22 -1 -1 36740 -1 -1 26 32 0 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 65256 32 32 280 312 1 205 90 17 17 289 -1 unnamed_device 25.2 MiB 0.38 1333 8934 2065 5975 894 63.7 MiB 0.05 0.00 5.73878 -118.225 -5.73878 5.73878 0.69 0.000204913 0.000161183 0.0122851 0.00992628 28 3896 47 6.55708e+06 313430 500653. 1732.36 6.24 0.108518 0.0905458 21310 115450 -1 3126 19 1420 4683 272679 61036 5.97918 5.97918 -137.471 -5.97918 0 0 612192. 2118.31 0.22 0.06 0.07 -1 -1 0.22 0.0158697 0.014317 186 185 -1 -1 -1 -1

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc
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k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.07 vpr 65.63 MiB -1 -1 0.23 21888 3 0.09 -1 -1 36916 -1 -1 68 99 1 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 67208 99 130 344 474 1 226 298 12 12 144 clb auto 26.7 MiB 0.06 572 76913 25305 39110 12498 65.6 MiB 0.15 0.00 1.64622 -105.715 -1.64622 1.64622 0.32 0.000482789 0.00044169 0.0349808 0.0312151 48 1085 10 5.66058e+06 4.21279e+06 394078. 2736.65 0.67 0.139468 0.12771 13382 75762 -1 1140 12 453 731 37358 11513 1.82553 1.82553 -130.835 -1.82553 -1.02001 -0.29768 503207. 3494.49 0.14 0.02 0.06 -1 -1 0.14 0.0173409 0.0162621 0.01093 0.2542 0.08242 0.6634
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k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 12.09 vpr 68.79 MiB -1 -1 0.36 26680 15 0.35 -1 -1 38504 -1 -1 41 162 0 5 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 70444 162 96 1009 950 1 703 304 16 16 256 mult_36 auto 30.7 MiB 0.22 5552 80963 22362 51673 6928 68.8 MiB 0.34 0.01 19.666 -1466.75 -19.666 19.666 0.59 0.00111782 0.000949189 0.101898 0.0913862 46 12189 28 1.21132e+07 4.18965e+06 727248. 2840.81 6.70 0.563123 0.513646 24972 144857 -1 9925 17 3215 6454 2159024 550134 22.1063 22.1063 -1720.05 -22.1063 0 0 934704. 3651.19 0.27 0.41 0.10 -1 -1 0.27 0.0797821 0.0752633 0.007677 0.3605 0.01701 0.6225
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k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 476.94 vpr 463.99 MiB -1 -1 45.55 352948 123 53.81 -1 -1 82308 -1 -1 1358 114 45 8 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 475128 114 102 21994 21904 1 11874 1627 50 50 2500 memory auto 194.7 MiB 16.49 160889 1072907 388128 662323 22456 428.7 MiB 18.69 0.16 67.3938 -48487.7 -67.3938 67.3938 21.69 0.0344996 0.0276502 3.0547 2.53338 96 251615 38 1.47946e+08 1.01019e+08 1.58254e+07 6330.17 245.76 14.6365 12.5049 343768 3324272 -1 220414 23 44834 170475 53274146 13930131 79.0394 79.0394 -67950.1 -79.0394 -13.0154 -0.296573 1.97871e+07 7914.84 6.59 14.23 2.35 -1 -1 6.59 2.04511 1.87317 0.08237 0.433 0.01151 0.5555

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