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changed the RR graph switch selection for wires with different directions
1 parent b4be0a5 commit 5ea2e53

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+17
-4
lines changed

1 file changed

+17
-4
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vpr/src/route/rr_graph2.cpp

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,8 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
300300
* as they will not be staggered by different segment start points. */
301301

302302
int cur_track, ntracks, itrack, length, j, index;
303-
int arch_wire_switch, arch_opin_switch, fac, num_sets, tmp;
303+
int fac, num_sets, tmp;
304+
int arch_wire_switch, arch_opin_switch, arch_wire_switch_dec, arch_opin_switch_dec;
304305
int arch_opin_between_dice_switch;
305306
int group_start, first_track;
306307
std::unique_ptr<int[]> sets_per_seg_type;
@@ -352,8 +353,10 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
352353

353354
arch_wire_switch = segment_inf[i].arch_wire_switch;
354355
arch_opin_switch = segment_inf[i].arch_opin_switch;
356+
arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec;
357+
arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec;
355358
arch_opin_between_dice_switch = segment_inf[i].arch_opin_between_dice_switch;
356-
VTR_ASSERT((arch_wire_switch == arch_opin_switch) || (directionality != UNI_DIRECTIONAL));
359+
VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL));
357360

358361
/* Set up the tracks of same type */
359362
group_start = 0;
@@ -416,8 +419,6 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
416419
seg_details[cur_track].Cmetal = segment_inf[i].Cmetal;
417420
//seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m;
418421

419-
seg_details[cur_track].arch_wire_switch = arch_wire_switch;
420-
seg_details[cur_track].arch_opin_switch = arch_opin_switch;
421422
seg_details[cur_track].arch_opin_between_dice_switch = arch_opin_between_dice_switch;
422423

423424
if (BI_DIRECTIONAL == directionality) {
@@ -427,6 +428,18 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
427428
seg_details[cur_track].direction = (itrack % 2) ? Direction::DEC : Direction::INC;
428429
}
429430

431+
//check for directionality to set the wire_switch and opin_switch
432+
//if not specified in the architecture file, we will use a same mux for both directions
433+
if (seg_details[cur_track].direction == Direction::INC || arch_wire_switch_dec == -1){
434+
seg_details[cur_track].arch_opin_switch = arch_opin_switch;
435+
seg_details[cur_track].arch_wire_switch = arch_wire_switch;
436+
}
437+
else {
438+
VTR_ASSERT(seg_details[cur_track].direction == Direction::DEC);
439+
seg_details[cur_track].arch_opin_switch = arch_opin_switch_dec;
440+
seg_details[cur_track].arch_wire_switch = arch_wire_switch_dec;
441+
}
442+
430443
seg_details[cur_track].index = i;
431444
seg_details[cur_track].abs_index = segment_inf[i].seg_index;
432445

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