[Infra]: - fix SPRAM/DPRAM VPR packing issue for circuits synthesized by Yosys

	 - fix a concatenation bug in arm_core caused failure in ABC for circuits synthesized by Yosys
	 - remove SPRAM/DPRAM rename files
	 - add info to Yosys synthesis script

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/benchmarks/verilog/arm_core.v

@@ -4048,7 +4048,7 @@ reg  [31:0] r11 = 32'hdeadbeef;
 reg  [31:0] r12 = 32'hdeadbeef;
 reg  [31:0] r13 = 32'hdeadbeef;
 reg  [31:0] r14 = 32'hdeadbeef;
-reg  [23:0] r15 = 24'hc0ffee;
+reg  [23:0] r15; // line: 4272
 
 wire  [31:0] r0_out;
 wire  [31:0] r1_out;
@@ -4268,7 +4268,8 @@ assign r15_out_rm_nxt = { i_status_bits_flags,
                           i_status_bits_firq_mask, 
                           i_pc, 
                           i_mode_exec};
- 
+
+// if r15 is initialized => Yosys+ABC:A CI/CO pair share the name (u_execute.u_register_bank.r15[1]) but do not link directly
 assign r15_out_rn     = {6'd0, r15, 2'd0};
 
 

vtr_flow/misc/synthesis.ys

@@ -1,4 +1,17 @@
-# XXX is replaced with filename by the run_vtr_flow script
+#################################################################
+# Yosys synthesis script, including generic 'synth' commands, 	#
+# in addition to techmap asynchronous FFs and VTR hard blocks.	#
+# Once the VTR flow runs with the Yosys front-end, Yosys        #
+# synthesizes the input design using the following commands. 	#
+#																#
+# NOTE: the script is adapted from the one Eddie Hung proposed 	#
+# for VTR-to-Bitstream[1]. However, a few minor changes to make	#
+# it adaptable with the current VTR flow have been made.		#
+#																#
+# [1] http://eddiehung.github.io/vtb.html						#
+#################################################################
+
+# XXX (input circuit) is replaced with filename by the run_vtr_flow script
 read_verilog -nolatches XXX
 
 # These commands follow the generic `synth'
@@ -66,6 +79,7 @@ read_verilog -lib DDD     #(DDD) will be replaced by dual_port_ram.v by python s
 read_verilog SSR         #(SSR) will be replaced by spram_rename.v by python script
 read_verilog DDR         #(DDR) will be replaced by dpram_rename.v by python script
 
+
 flatten
 # Lastly, check the hierarchy for any unknown modules,
 # and purge all modules (including blackboxes) that
@@ -78,4 +92,4 @@ tee -o /dev/stdout stat
 # the internal `$true'/`$false' signals vcc/gnd, but
 # switch `-impltf' doesn't output them
 # ZZZ will be replaced by run_vtr_flow.pl
-write_blif -true - vcc -false - gnd -undef - unconn -blackbox ZZZ
+write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

vtr_flow/misc/yosyslib/dpram_rename.v

@@ -5,7 +5,7 @@
 
 // depth and data may need to be splited
 module dualPortRam(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
-    parameter ADDR_WIDTH = 1;
+    parameter ADDR_WIDTH = `MEM_MAXADDR;
     parameter DATA_WIDTH = 1;
 
     input clk;
@@ -57,4 +57,4 @@ module dual_port_ram(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
         out2 <= RAM[addr2];
     end
     */
-endmodule
+endmodule

vtr_flow/misc/yosyslib/dual_port_ram.v

@@ -5,7 +5,7 @@
 
 // depth and data may need to be splited
 module dual_port_ram(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
-    parameter ADDR_WIDTH = 1;
+    parameter ADDR_WIDTH = `MEM_MAXADDR;
     parameter DATA_WIDTH = 1;
 
     input clk;
@@ -108,3 +108,4 @@ module dualPortRam(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
     end
     */
 endmodule
+

vtr_flow/misc/yosyslib/single_port_ram.v

@@ -6,7 +6,7 @@
 // depth and data may need to be splited
 module single_port_ram(clk, we, addr, data, out);
 
-    parameter ADDR_WIDTH = 1;
+    parameter ADDR_WIDTH = `MEM_MAXADDR;
     parameter DATA_WIDTH = 1;
 
     input clk;
@@ -89,3 +89,4 @@ module singlePortRam(clk, data, addr, we, out);
     end
     */
 endmodule
+

vtr_flow/misc/yosyslib/spram_rename.v

@@ -1,9 +1,12 @@
 `timescale 1ps/1ps
 
+`define MEM_MAXADDR PPP
+`define MEM_MAXDATA 36
+
 // depth and data may need to be splited
 module singlePortRam(clk, we, addr, data, out);
 
-    parameter ADDR_WIDTH = 1;
+    parameter ADDR_WIDTH = `MEM_MAXADDR;
     parameter DATA_WIDTH = 1;
 
     input clk;
@@ -46,4 +49,4 @@ module single_port_ram(clk, data, addr, we, out);
         out <= RAM[addr];
     end
     */
-endmodule
+endmodule

vtr_flow/tasks/regression_tests/regression_test.ods

@@ -45,4 +45,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -start yosys
+script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 -start yosys