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1 | 1 | arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets |
2 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 74.18 vpr 67.70 MiB -1 -1 0.14 17128 1 0.05 -1 -1 32144 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69324 6 1 16 17 2 10 9 17 17 289 -1 auto 29.2 MiB 0.10 67 27 9 18 0 67.7 MiB 0.01 0.00 1.66771 -4.34981 -1.66771 0.805 14.84 0.000465591 0.000362362 0.00280543 0.00236583 20 141 4 1.34605e+07 107788 411619. 1424.29 33.41 0.0222166 0.0183417 24098 82050 -1 132 2 10 10 10345 2735 2.73969 0.805 -5.54288 -2.73969 -0.842296 -0.421627 535376. 1852.51 3.02 4.92 1.80 -1 -1 3.02 0.00712665 0.00644851 1 9 |
3 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 39.92 vpr 67.36 MiB -1 -1 0.12 16896 1 0.02 -1 -1 29976 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68972 3 1 5 6 1 4 5 13 13 169 -1 auto 28.9 MiB 0.03 26 12 4 8 0 67.4 MiB 0.01 0.00 0.684768 -1.31529 -0.684768 0.684768 7.66 0.000145249 0.000107804 0.000912111 0.000756221 20 52 1 6.63067e+06 53894 227243. 1344.63 17.97 0.00522005 0.00428397 13251 44387 -1 54 1 4 4 4093 1283 1.57879 1.57879 -1.64658 -1.57879 -0.385237 -0.385237 294987. 1745.49 1.62 2.64 0.97 -1 -1 1.62 0.00213645 0.00194794 0 4 |
4 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 75.45 vpr 67.44 MiB -1 -1 0.13 17128 1 0.05 -1 -1 32000 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69056 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.10 86 27 10 16 1 67.4 MiB 0.01 0.00 1.73508 -4.45965 -1.73508 0.805 14.86 0.000467564 0.000363489 0.00253116 0.00209264 20 156 3 1.34605e+07 107788 424167. 1467.71 34.10 0.0264007 0.0217019 24098 84646 -1 143 1 9 9 10051 2608 2.60696 0.805 -5.45498 -2.60696 -0.46436 -0.232734 547923. 1895.93 3.00 4.91 1.82 -1 -1 3.00 0.0058344 0.00529701 1 9 |
5 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 40.03 vpr 67.21 MiB -1 -1 0.12 17012 1 0.02 -1 -1 29904 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68828 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.03 26 12 4 8 0 67.2 MiB 0.01 0.00 0.698051 -1.3327 -0.698051 0.698051 7.93 0.000142967 0.00010535 0.000901405 0.000744567 20 52 1 6.63067e+06 53894 235789. 1395.20 18.41 0.00525922 0.0042924 13251 46155 -1 54 1 4 4 4037 1263 1.58964 1.58964 -1.65632 -1.58964 -0.386343 -0.386343 303533. 1796.05 1.66 2.71 1.01 -1 -1 1.66 0.00212216 0.00193398 0 4 |
6 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 74.59 vpr 67.81 MiB -1 -1 0.14 16948 1 0.05 -1 -1 32132 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69440 6 1 16 17 2 10 9 17 17 289 -1 auto 29.2 MiB 0.10 67 27 9 18 0 67.8 MiB 0.01 0.00 1.66771 -4.34981 -1.66771 0.805 14.86 0.00046856 0.000365172 0.00281248 0.00237262 20 619 3 1.34605e+07 107788 408865. 1414.76 33.53 0.0204852 0.0169571 24098 82150 -1 610 2 10 10 12597 4156 3.681 0.805 -7.42729 -3.681 -2.7249 -1.36293 532630. 1843.01 3.06 4.99 1.80 -1 -1 3.06 0.00669788 0.00599603 1 9 |
7 | | -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 39.06 vpr 67.42 MiB -1 -1 0.12 16968 1 0.02 -1 -1 29828 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69036 3 1 5 6 1 4 5 13 13 169 -1 auto 28.9 MiB 0.03 26 12 4 8 0 67.4 MiB 0.01 0.00 0.684768 -1.31529 -0.684768 0.684768 7.60 0.000142626 0.000105207 0.000839515 0.000682556 20 183 1 6.63067e+06 53894 225153. 1332.26 17.38 0.00516117 0.00422186 13251 44463 -1 185 1 4 4 1139 237 2.19802 2.19802 -2.19802 -2.19802 -1.00447 -1.00447 292904. 1733.16 1.53 2.55 0.98 -1 -1 1.53 0.00214788 0.00195713 0 4 |
| 2 | +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.80 vpr 62.41 MiB -1 -1 0.15 16964 1 0.23 -1 -1 31908 -1 -1 2 6 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63912 6 1 16 17 2 10 9 17 17 289 -1 auto 23.9 MiB 0.02 67 27 9 18 0 62.4 MiB 0.00 0.00 1.66771 -4.34981 -1.66771 0.805 0.93 6.292e-05 5.3006e-05 0.00038211 0.000333692 20 141 4 1.34605e+07 107788 411619. 1424.29 0.56 0.00244758 0.00222679 24098 82050 -1 132 2 10 10 10345 2735 2.73969 0.805 -5.54288 -2.73969 -0.842296 -0.421627 535376. 1852.51 0.16 0.28 0.12 -1 -1 0.16 0.00169603 0.00160376 1 9 |
| 3 | +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.27 vpr 62.22 MiB -1 -1 0.17 16808 1 0.23 -1 -1 29760 -1 -1 1 3 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63712 3 1 5 6 1 4 5 13 13 169 -1 auto 23.5 MiB 0.01 26 12 4 8 0 62.2 MiB 0.00 0.00 0.684768 -1.31529 -0.684768 0.684768 0.50 2.4726e-05 1.8709e-05 0.000144623 0.000117099 20 52 1 6.63067e+06 53894 227243. 1344.63 0.31 0.0012983 0.00120858 13251 44387 -1 54 1 4 4 4093 1283 1.57879 1.57879 -1.64658 -1.57879 -0.385237 -0.385237 294987. 1745.49 0.08 0.16 0.07 -1 -1 0.08 0.00115216 0.00111231 0 4 |
| 4 | +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.85 vpr 62.34 MiB -1 -1 0.17 17132 1 0.23 -1 -1 32004 -1 -1 2 6 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63832 6 1 16 17 2 10 9 17 17 289 -1 auto 23.8 MiB 0.02 86 27 10 16 1 62.3 MiB 0.00 0.00 1.73508 -4.45965 -1.73508 0.805 0.94 6.3063e-05 5.3154e-05 0.000382365 0.000334342 20 156 3 1.34605e+07 107788 424167. 1467.71 0.57 0.00232866 0.0021239 24098 84646 -1 143 1 9 9 10051 2608 2.60696 0.805 -5.45498 -2.60696 -0.46436 -0.232734 547923. 1895.93 0.16 0.29 0.12 -1 -1 0.16 0.00170576 0.00163038 1 9 |
| 5 | +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.23 vpr 62.38 MiB -1 -1 0.17 17164 1 0.23 -1 -1 29612 -1 -1 1 3 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63872 3 1 5 6 1 4 5 13 13 169 -1 auto 23.9 MiB 0.01 26 12 4 8 0 62.4 MiB 0.00 0.00 0.698051 -1.3327 -0.698051 0.698051 0.51 2.4972e-05 1.869e-05 0.000139687 0.000111725 20 52 1 6.63067e+06 53894 235789. 1395.20 0.32 0.00137232 0.0012738 13251 46155 -1 54 1 4 4 4037 1263 1.58964 1.58964 -1.65632 -1.58964 -0.386343 -0.386343 303533. 1796.05 0.08 0.12 0.04 -1 -1 0.08 0.00117266 0.00113601 0 4 |
| 6 | +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.90 vpr 62.34 MiB -1 -1 0.16 17264 1 0.23 -1 -1 31964 -1 -1 2 6 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63832 6 1 16 17 2 10 9 17 17 289 -1 auto 23.8 MiB 0.02 67 27 9 18 0 62.3 MiB 0.01 0.00 1.66771 -4.34981 -1.66771 0.805 0.97 6.398e-05 5.3905e-05 0.000660909 0.000612393 20 619 3 1.34605e+07 107788 408865. 1414.76 0.59 0.00267306 0.00246585 24098 82150 -1 610 2 10 10 12597 4156 3.681 0.805 -7.42729 -3.681 -2.7249 -1.36293 532630. 1843.01 0.16 0.29 0.12 -1 -1 0.16 0.00169111 0.00160117 1 9 |
| 7 | +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.27 vpr 62.18 MiB -1 -1 0.16 16892 1 0.23 -1 -1 29700 -1 -1 1 3 0 0 success v8.0.0-10229-g9de163162 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-03T20:58:32 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63672 3 1 5 6 1 4 5 13 13 169 -1 auto 23.6 MiB 0.01 26 12 4 8 0 62.2 MiB 0.00 0.00 0.684768 -1.31529 -0.684768 0.684768 0.50 2.4929e-05 1.8673e-05 0.000144104 0.000115519 20 183 1 6.63067e+06 53894 225153. 1332.26 0.31 0.00152207 0.00139859 13251 44463 -1 185 1 4 4 1139 237 2.19802 2.19802 -2.19802 -2.19802 -1.00447 -1.00447 292904. 1733.16 0.08 0.15 0.07 -1 -1 0.08 0.00115607 0.00111789 0 4 |
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