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[test] add strong 3d
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‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt

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#
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############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
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# Path to directory of SDC files to use
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sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
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# Path to directory of architectures to use
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archs_dir=arch/multi_die/stratixiv_3d
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# Add circuits to list to sweep
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circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif
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# Add architectures to list to sweep
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arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml
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arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
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# Parse info and how to parse
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parse_file=vpr_titan.txt
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# How to parse QoR info
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qor_parse_file=qor_vpr_titan.txt
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# Pass requirements
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pass_requirements_file=pass_requirements_vpr_titan.txt
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script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map
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script_params_list_add = --place_bounding_box_mode auto_bb
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script_params_list_add = --place_bounding_box_mode cube_bb
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script_params_list_add = --place_bounding_box_mode per_layer_bb
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‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
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3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 83.45 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421664 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.4 MiB 12.25 180137 58272 230944 40790 173771 16383 1388.3 MiB 10.48 0.15 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0444933 0.0387879 3.15031 2.6241 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 12.21 -1 -1 1388.3 MiB 10.28 4.91142 4.17713 1388.3 MiB -1 16.75
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3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 85.51 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421424 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 12.33 180137 58272 230944 40790 173771 16383 1388.1 MiB 10.48 0.14 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0434223 0.0377288 3.13504 2.6098 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 13.53 -1 -1 1388.1 MiB 10.72 4.93468 4.19984 1388.1 MiB -1 17.21
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3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 86.05 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421572 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 12.02 186170 63595 242080 43083 181450 17547 1388.3 MiB 12.05 0.17 5.04678 4.86192 -4242.28 -3.86192 2.41884 0.05 0.051916 0.0457829 3.35985 2.75261 103428 8.31615 32795 2.63689 27768 38066 44034475 9785894 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 5.18643 2.65983 -5392.13 -4.18642 0 0 13.06 -1 -1 1388.3 MiB 9.86 5.14157 4.32891 1388.3 MiB -1 18.69
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3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 57.03 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245688 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.9 MiB 11.85 186170 63157 219808 34278 166444 19086 1216.5 MiB 10.07 0.18 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0545904 0.0489007 2.99902 2.51676 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.46 -1 -1 1216.5 MiB 4.58 4.95133 4.23051 1216.5 MiB -1 1.96
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3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 56.04 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245528 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 11.88 180137 61714 223520 36703 169137 17680 1216.3 MiB 10.63 0.16 5.41016 4.96403 -5546.44 -3.96403 2.84288 0.01 0.0440263 0.0385965 3.36781 2.8222 75346 6.05821 18897 1.51942 26061 36573 12725206 1711712 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.08769 2.56235 -5100.1 -4.08769 0 0 7.77 -1 -1 1216.3 MiB 4.84 5.1781 4.41964 1216.3 MiB -1 1.92
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3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 58.79 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245324 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 11.84 186170 63157 219808 34278 166444 19086 1216.1 MiB 10.25 0.14 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0422071 0.0368357 2.98723 2.48631 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.89 -1 -1 1216.1 MiB 4.79 4.83395 4.11932 1216.1 MiB -1 1.80

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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regression_tests/vtr_reg_strong/strong_noc
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regression_tests/vtr_reg_strong/strong_flat_router
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regression_tests/vtr_reg_strong/strong_routing_constraints
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regression_tests/vtr_reg_strong/strong_3d

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