Merge pull request #1883 from ArashAhmadian/S10_diff_x_y_channels

Generalizing channels & segments to horizontal and vertical in rr_graph

Author: vaughnbetz

libs/libarchfpga/src/physical_types.h

@@ -1442,7 +1442,12 @@ enum e_Fc_type {
  * Cmetal: Capacitance of a routing track, per unit logic block length.      *
  * Rmetal: Resistance of a routing track, per unit logic block length.       *
  * (UDSD by AY) drivers: How do signals driving a routing track connect to   *
- *                       the track?                                          *
+ *                       the track?  
+ * seg_index: The index of the segment as stored in the appropriate Segs list*
+ *            Upon loading the architecture, we use this field to keep track *
+ *            the segment's index in the unified segment_inf vector. This is *
+ *            usefull when building the rr_graph for different Y & X channels*
+ *            interms of track distribution and segment type.                *
  * meta: Table storing extra arbitrary metadata attributes.                  */
 struct t_segment_inf {
     std::string name;
@@ -1459,14 +1464,27 @@ struct t_segment_inf {
     enum e_parallel_axis parallel_axis;
     std::vector<bool> cb;
     std::vector<bool> sb;
-
+    int seg_index;
     //float Cmetal_per_m; /* Wire capacitance (per meter) */
 };
 
 inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) {
-    return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.cb == b.cb && a.sb == b.sb;
+    return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb;
 }
 
+/*provide hashing for t_segment_inf to enable the use of many std containers.
+ * Only the most important/varying fields are used (not worth the extra overhead to include all fields)*/
+
+struct t_hash_segment_inf {
+    size_t operator()(const t_segment_inf& seg_inf) const noexcept {
+        size_t result;
+        result = ((((std::hash<std::string>()(seg_inf.name)
+                     ^ std::hash<int>()(seg_inf.frequency) << 10)
+                    ^ std::hash<int>()(seg_inf.length) << 20)
+                   ^ std::hash<int>()((int)seg_inf.arch_opin_switch) << 30));
+        return result;
+    }
+};
 enum class SwitchType {
     MUX = 0,   //A configurable (buffered) mux (single-driver)
     TRISTATE,  //A configurable tristate-able buffer (multi-driver)

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -3702,6 +3702,8 @@ static void ProcessSegments(pugi::xml_node Parent,
             ProcessCB_SB(SubElem, Segs[i].sb, loc_data);
         }
 
+        /*Store the index of this segment in Segs vector*/
+        Segs[i].seg_index = i;
         /* Get next Node */
         Node = Node.next_sibling(Node.name());
     }

vpr/src/base/echo_files.cpp

@@ -71,7 +71,6 @@ void alloc_and_load_echo_file_info() {
     }
 
     setAllEchoFileEnabled(getEchoEnabled());
-
     //User input nelist
     setEchoFileName(E_ECHO_ATOM_NETLIST_ORIG, "atom_netlist.orig.echo.blif");
     setEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED, "atom_netlist.cleaned.echo.blif");
@@ -86,6 +85,7 @@ void alloc_and_load_echo_file_info() {
     setEchoFileName(E_ECHO_INTRA_LB_FAILED_ROUTE, "intra_lb_failed_route.echo");
 
     //Timing Graphs
+    setEchoFileName(E_ECHO_TRACK_TO_PIN_MAP, "track_to_pin_map.echo");
     setEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH, "timing_graph.pre_pack.echo");
     setEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH, "timing_graph.place_initial.echo");
     setEchoFileName(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH, "timing_graph.place_final.echo");
@@ -124,6 +124,7 @@ void alloc_and_load_echo_file_info() {
     setEchoFileName(E_ECHO_SEG_DETAILS, "seg_details.txt");
     setEchoFileName(E_ECHO_CHAN_DETAILS, "chan_details.txt");
     setEchoFileName(E_ECHO_SBLOCK_PATTERN, "sblock_pattern.txt");
+    setEchoFileName(E_ECHO_TRACK_TO_PIN_MAP, "track_to_pin_map.echo");
     setEchoFileName(E_ECHO_ENDPOINT_TIMING, "endpoint_timing.echo.json");
     setEchoFileName(E_ECHO_LOOKAHEAD_MAP, "lookahead_map.echo");
     setEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA, "rr_indexed_data.echo");

vpr/src/base/echo_files.h

@@ -2,6 +2,7 @@
 #define ECHO_FILES_H
 
 enum e_echo_files {
+
     //Input netlist
     E_ECHO_ATOM_NETLIST_ORIG,
     E_ECHO_ATOM_NETLIST_CLEANED,
@@ -49,6 +50,7 @@ enum e_echo_files {
     E_ECHO_SEG_DETAILS,
     E_ECHO_CHAN_DETAILS,
     E_ECHO_SBLOCK_PATTERN,
+    E_ECHO_TRACK_TO_PIN_MAP,
     E_ECHO_ENDPOINT_TIMING,
     E_ECHO_LOOKAHEAD_MAP,
     E_ECHO_RR_GRAPH_INDEXED_DATA,

vpr/src/base/place_and_route.cpp

@@ -430,15 +430,15 @@ t_chan_width init_chan(int cfactor, t_chan_width_dist chan_width_dist, t_graph_t
     chan_width.x_max = chan_width.y_max = INT_MIN;
     chan_width.x_min = chan_width.y_min = INT_MAX;
     for (size_t i = 0; i < grid.height(); ++i) {
-        chan_width.max = std::max(chan_width.max, chan_width.x_list[i]);
         chan_width.x_max = std::max(chan_width.x_max, chan_width.x_list[i]);
         chan_width.x_min = std::min(chan_width.x_min, chan_width.x_list[i]);
     }
+    chan_width.max = std::max(chan_width.max, chan_width.x_max);
     for (size_t i = 0; i < grid.width(); ++i) {
-        chan_width.max = std::max(chan_width.max, chan_width.y_list[i]);
         chan_width.y_max = std::max(chan_width.y_max, chan_width.y_list[i]);
         chan_width.y_min = std::min(chan_width.y_min, chan_width.y_list[i]);
     }
+    chan_width.max = std::max(chan_width.max, chan_width.y_max);
 
 #ifdef VERBOSE
     VTR_LOG("\n");

vpr/src/base/vpr_types.h

@@ -109,10 +109,11 @@ constexpr auto INVALID_BLOCK_ID = ClusterBlockId(-2);
 #endif
 
 enum class e_router_lookahead {
-    CLASSIC,      ///<VPR's classic lookahead (assumes uniform wire types)
-    MAP,          ///<Lookahead considering different wire types (see Oleg Petelin's MASc Thesis)
-    EXTENDED_MAP, ///<Lookahead with a more extensive node sampling method
-    NO_OP         ///<A no-operation lookahead which always returns zero
+    DONT_CARE = -1, /// AA: Used for when we don't care about the lookahead type, e.g. when serializing the rr_graph.
+    CLASSIC,        ///<VPR's classic lookahead (assumes uniform wire types)
+    MAP,            ///<Lookahead considering different wire types (see Oleg Petelin's MASc Thesis)
+    EXTENDED_MAP,   ///<Lookahead with a more extensive node sampling method
+    NO_OP           ///<A no-operation lookahead which always returns zero
 };
 
 enum class e_route_bb_update {
@@ -1344,6 +1345,20 @@ struct t_det_routing_arch {
  *   @param Rmetal     Resistance of a routing track, per unit logic block length.
  *   @param direction  The direction of a routing track.
  *   @param index      index of the segment type used for this track.
+ *                     Note that this index will store the index of the segment
+ *                     relative to its **parallel** segment types, not all segments
+ *                     as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph
+ *                     for details but here is an example: say our segment_inf_vec in 
+ *                     device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y]
+ *                     when building the rr_graph, static segment_inf_vectors will be 
+ *                     created for each direction, thus you will have the following 
+ *                     2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. 
+ *                     As a result, e.g. seg_b_y::index == 1 (index in Y_vec) 
+ *                     and != 3 (index in device_ctx segment_inf_vec).
+ *   @param abs_index  index is relative to the segment_inf vec as stored in device_ctx. 
+ *                     Note that the above vector is **unifies** both x-parallel and 
+ *                     y-parallel segments and is loaded up originally in read_xml_arch_file.cpp 
+ * 
  *   @param type_name_ptr  pointer to name of the segment type this track belongs
  *                     to. points to the appropriate name in s_segment_inf
  */
@@ -1364,6 +1379,7 @@ struct t_seg_details {
     int seg_start = 0;
     int seg_end = 0;
     int index = 0;
+    int abs_index = 0;
     float Cmetal_per_m = 0; ///<Used for power
     std::string type_name;
 };
@@ -1399,6 +1415,7 @@ class t_chan_seg_details {
     Direction direction() const { return seg_detail_->direction; }
 
     int index() const { return seg_detail_->index; }
+    int abs_index() const { return seg_detail_->abs_index; }
 
     const vtr::string_view type_name() const {
         return vtr::string_view(
@@ -1425,7 +1442,9 @@ class t_chan_seg_details {
     const t_seg_details* seg_detail_ = nullptr;
 };
 
-/* Defines a 2-D array of t_seg_details data structures (one per channel)   */
+/* Defines a 3-D array of t_chan_seg_details data structures (one per-each horizontal and vertical channel)   
+ * once allocated in rr_graph2.cpp, is can be accessed like: [0..grid.width()][0..grid.height()][0..num_tracks-1]
+ */
 typedef vtr::NdMatrix<t_chan_seg_details, 3> t_chan_details;
 
 /**
@@ -1585,7 +1604,17 @@ struct t_power_opts {
     bool do_power; ///<Perform power estimation?
 };
 
-///@brief Channel width data
+/** @brief Channel width data
+ * @param max= Maximum channel width between x_max and y_max. 
+ * @param x_min= Minimum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp 
+ * @param y_min= Same as above but for vertical channels. 
+ * @param x_max= Maximum channel width of horiozntal channels. Initialized when init_chan() is invoked in rr_graph2.cpp 
+ * @param y_max= Same as above but for vertical channels. 
+ * @param x_list= Stores the channel width of all horizontal channels and thus goes from [0..grid.height()] 
+ * (imagine a 2D Cartesian grid with horizontal lines starting at every grid point on a line parallel to the y-axis)
+ * @param y_list= Stores the channel width of all verical channels and thus goes from [0..grid.width()]
+ * (imagine a 2D Cartesian grid with vertical lines starting at every grid point on a line parallel to the x-axis)
+ */
 struct t_chan_width {
     int max = 0;
     int x_max = 0;

vpr/src/route/build_switchblocks.cpp

@@ -232,7 +232,8 @@ static void compute_wire_connections(
     const t_chan_details& chan_details_y,
     t_switchblock_inf* sb,
     const DeviceGrid& grid,
-    const t_wire_type_sizes* wire_type_sizes,
+    const t_wire_type_sizes* wire_type_sizes_x,
+    const t_wire_type_sizes* wire_type_sizes_y,
     e_directionality directionality,
     t_sb_connection_map* sb_conns,
     vtr::RandState& rand_state,
@@ -251,7 +252,8 @@ static void compute_wireconn_connections(
     int to_y,
     t_rr_type from_chan_type,
     t_rr_type to_chan_type,
-    const t_wire_type_sizes* wire_type_sizes,
+    const t_wire_type_sizes* wire_type_sizes_x,
+    const t_wire_type_sizes* wire_type_sizes_y,
     const t_switchblock_inf* sb,
     t_wireconn_inf* wireconn_ptr,
     t_sb_connection_map* sb_conns,
@@ -317,7 +319,9 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail
     /* Holds temporary memory for parsing. */
     t_wireconn_scratchpad scratchpad;
 
-    /* get a single number for channel width */
+    /* get a single number for channel width. 
+     * AA: Note that this needs be changed to support different horizontal and vertical channels. Future action item ... */
+
     int channel_width = nodes_per_chan->max;
     if (nodes_per_chan->max != nodes_per_chan->x_min || nodes_per_chan->max != nodes_per_chan->y_min) {
         VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Custom switch blocks currently support consistent channel widths only.");
@@ -329,7 +333,21 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail
     /* We assume that x & y channels have the same ratios of wire types. i.e., looking at a single
      * channel is representative of all channels in the FPGA -- as of 3/9/2013 this is true in VPR */
     t_wire_type_sizes wire_type_sizes;
-    count_wire_type_sizes(chan_details_x[0][0].data(), channel_width, &wire_type_sizes);
+    t_wire_type_sizes wire_type_sizes_x;
+    t_wire_type_sizes wire_type_sizes_y;
+
+    /* Count the number of wires in each wire type in the specified channel. Note that this is representative of
+     * the wire count for every channel in direction due to the assumption stated above. 
+     * AA: This will not hold if we 
+     *     1) support different horizontal and vertical segment distributions
+     *     2) support non-uniform channel distributions. 
+     * 
+     * Future action item ...
+     */
+
+    count_wire_type_sizes(chan_details_y[0][0].data(), nodes_per_chan->y_max, &wire_type_sizes_y);
+    count_wire_type_sizes(chan_details_x[0][0].data(), nodes_per_chan->x_max, &wire_type_sizes_x);
+    count_wire_type_sizes(chan_details_x[0][0].data(), nodes_per_chan->max, &wire_type_sizes);
 
 #ifdef FAST_SB_COMPUTATION
     /******** fast switch block computation method; computes a row of switchblocks then stamps it out everywhere ********/
@@ -351,6 +369,9 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail
                                    grid, &wire_type_sizes, directionality, &sb_row, sb_conns);
 
 #else
+
+    //channel_width is only used in FAST_SB_COMPUTATION, do below so it doesn't throw a compile warning.
+    (void)channel_width;
     /******** slow switch block computation method; computes switchblocks at each coordinate ********/
     /* iterate over all the switchblocks specified in the architecture */
     for (int i_sb = 0; i_sb < (int)switchblocks.size(); i_sb++) {
@@ -373,7 +394,7 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail
                          * the current wire will connect to */
                         compute_wire_connections(x_coord, y_coord, from_side, to_side,
                                                  chan_details_x, chan_details_y, &sb, grid,
-                                                 &wire_type_sizes, directionality, sb_conns, rand_state, &scratchpad);
+                                                 &wire_type_sizes_x, &wire_type_sizes_y, directionality, sb_conns, rand_state, &scratchpad);
                     }
                 }
             }
@@ -758,7 +779,7 @@ static void get_switchpoint_wires(
 
 /* Compute the wire(s) that the wire at (x, y, from_side, to_side) should connect to.
  * sb_conns is updated with the result */
-static void compute_wire_connections(int x_coord, int y_coord, enum e_side from_side, enum e_side to_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, t_switchblock_inf* sb, const DeviceGrid& grid, const t_wire_type_sizes* wire_type_sizes, e_directionality directionality, t_sb_connection_map* sb_conns, vtr::RandState& rand_state, t_wireconn_scratchpad* scratchpad) {
+static void compute_wire_connections(int x_coord, int y_coord, enum e_side from_side, enum e_side to_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, t_switchblock_inf* sb, const DeviceGrid& grid, const t_wire_type_sizes* wire_type_sizes_x, const t_wire_type_sizes* wire_type_sizes_y, e_directionality directionality, t_sb_connection_map* sb_conns, vtr::RandState& rand_state, t_wireconn_scratchpad* scratchpad) {
     int from_x, from_y;                     /* index into source channel */
     int to_x, to_y;                         /* index into destination channel */
     t_rr_type from_chan_type, to_chan_type; /* the type of channel - i.e. CHANX or CHANY */
@@ -793,6 +814,14 @@ static void compute_wire_connections(int x_coord, int y_coord, enum e_side from_
         return;
     }
 
+    const t_wire_type_sizes* wire_type_sizes_from = wire_type_sizes_x;
+    const t_wire_type_sizes* wire_type_sizes_to = wire_type_sizes_x;
+    if (from_chan_type == CHANY) {
+        wire_type_sizes_from = wire_type_sizes_y;
+    }
+    if (to_chan_type == CHANY) {
+        wire_type_sizes_to = wire_type_sizes_y;
+    }
     /* iterate over all the wire connections specified for this switch block */
     for (int iconn = 0; iconn < (int)sb->wireconns.size(); iconn++) {
         /* pointer to a connection specification between wire types/subsegment_nums */
@@ -801,8 +830,8 @@ static void compute_wire_connections(int x_coord, int y_coord, enum e_side from_
         /* compute the destination wire segments to which the source wire segment should connect based on the
          * current wireconn */
         compute_wireconn_connections(grid, directionality, from_chan_details, to_chan_details,
-                                     sb_conn, from_x, from_y, to_x, to_y, from_chan_type, to_chan_type, wire_type_sizes,
-                                     sb, wireconn_ptr, sb_conns, rand_state, scratchpad);
+                                     sb_conn, from_x, from_y, to_x, to_y, from_chan_type, to_chan_type, wire_type_sizes_from,
+                                     wire_type_sizes_to, sb, wireconn_ptr, sb_conns, rand_state, scratchpad);
     }
 
     return;
@@ -824,7 +853,8 @@ static void compute_wireconn_connections(
     int to_y,
     t_rr_type from_chan_type,
     t_rr_type to_chan_type,
-    const t_wire_type_sizes* wire_type_sizes,
+    const t_wire_type_sizes* wire_type_sizes_from,
+    const t_wire_type_sizes* wire_type_sizes_to,
     const t_switchblock_inf* sb,
     t_wireconn_inf* wireconn_ptr,
     t_sb_connection_map* sb_conns,
@@ -836,12 +866,12 @@ static void compute_wireconn_connections(
 
     get_switchpoint_wires(grid,
                           from_chan_details[from_x][from_y].data(), from_chan_type, from_x, from_y, sb_conn.from_side,
-                          wireconn_ptr->from_switchpoint_set, wire_type_sizes, false, wireconn_ptr->from_switchpoint_order, rand_state,
+                          wireconn_ptr->from_switchpoint_set, wire_type_sizes_from, false, wireconn_ptr->from_switchpoint_order, rand_state,
                           &scratchpad->potential_src_wires,
                           &scratchpad->scratch_wires);
     get_switchpoint_wires(grid,
                           to_chan_details[to_x][to_y].data(), to_chan_type, to_x, to_y, sb_conn.to_side,
-                          wireconn_ptr->to_switchpoint_set, wire_type_sizes, true, wireconn_ptr->to_switchpoint_order, rand_state, &scratchpad->potential_dest_wires,
+                          wireconn_ptr->to_switchpoint_set, wire_type_sizes_to, true, wireconn_ptr->to_switchpoint_order, rand_state, &scratchpad->potential_dest_wires,
                           &scratchpad->scratch_wires);
 
     const auto& potential_src_wires = scratchpad->potential_src_wires;