Merge pull request #2215 from CAS-Atlantic/yosys_parmys_23

Add Support for Parmys plugin in VTR/Yosys

Author: vaughnbetz

.github/workflows/test.yml

@@ -35,6 +35,7 @@ jobs:
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON", extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON",     extra_pkgs: ""}
+          - {test: "vtr_reg_yosys_parmys",  cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_PARMYS_PLUGIN=ON",      extra_pkgs: ""}
           - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON", extra_pkgs: ""}
           - {test: "odin_tech_strong",      cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON",                           extra_pkgs: ""}
           - {test: "odin_reg_strong",       cores: "16", options: "",          cmake: "",                                              extra_pkgs: ""}

CMakeLists.txt

@@ -57,6 +57,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 option(WITH_YOSYS "Enable building Yosys" OFF)
 option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
 option(YOSYS_SV_UHDM_PLUGIN "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
+option(YOSYS_PARMYS_PLUGIN "Enable building and installing Parmys (Partial Mapper for Yosys) plugin" OFF)
 
 set(VTR_VERSION_MAJOR 8)
 set(VTR_VERSION_MINOR 1)
@@ -416,6 +417,13 @@ if(${YOSYS_SV_UHDM_PLUGIN})
     endif()
 endif()
 
+# check YOSYS_PARMYS_PLUGIN flag
+if(${YOSYS_PARMYS_PLUGIN})
+    if(NOT ${WITH_YOSYS})
+        message(SEND_ERROR "Using YOSYS_PARMYS_PLUGIN requires activating Yosys frontend. Please set WITH_YOSYS.")
+    endif()
+endif()
+
 #Add extra compilation flags to suppress warnings from some libraries/tools
 # Note that target_compile_options() *appends* to the current compilation options of
 # the specified target

ODIN_II/regression_test/tools/run_yosys.sh

@@ -43,6 +43,7 @@ _YOSYS_EXEC="${VTR_DIR}/Yosys/bin/yosys"
 _SURELOG_EXEC="${VTR_DIR}/Yosys/bin/surelog"
 _UHDM_DUMP_EXEC="${VTR_DIR}/Yosys/bin/uhdm-dump"
 _UHDM_HIER_EXEC="${VTR_DIR}/Yosys/bin/uhdm-hier"
+_PARMYS_PLUGIN_EXEC="${VTR_DIR}/Yosys/share/yosys/plugins/parmys.so"
 _INPUT_TYPE=""
 _TEST_INPUT_LIST=()
 _INPUT_LIST=()
@@ -461,6 +462,12 @@ function run_single_hdl() {
                 _exit_with_code "-1"
         esac
 
+        if [ -f "${_PARMYS_PLUGIN_EXEC}" ]
+        then
+            export MAPPER="parmys";
+        else
+            export MAPPER="yosys";
+        fi
 
         if [ -f "${OUTPUT_BLIF_PATH}/${TCL_BLIF_NAME}" ]; then
             print_test_stat "E"

README.developers.md

@@ -310,6 +310,7 @@ will be triggered. The following tests are included in the workflow:
 * [vtr_reg_nightly_test1-3](#vtr_reg_nightly_test1-3)
 * [vtr_reg_strong](#vtr_reg_strong)
 * vtr_reg_yosys
+* vtr_reg_yosys_parmys
 * vtr_reg_yosys_odin
 * odin_tech_strong
 * odin_reg_strong

doc/src/vtr/run_vtr_flow.rst

@@ -96,7 +96,14 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
 
 Running the default VTR flow using the Yosys standalone front-end.
 The Yosys HDL parser is considered as Yosys-SystemVerilog plugin (i.e., ``read_systemverilog``) and Yosys UHDM plugin (i.e., ``read_uhdm``), respectively.
-It is worth mentioning that utilizing Yosys plugins requires passing the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` compile flag to build and install the plugins for the Yosys front-end. 
+It is worth mentioning that utilizing Yosys plugins requires passing the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` compile flag to build and install the plugins for the Yosys front-end.
+
+.. code-block:: bash
+
+    # Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -start yosys -mapper parmys
+
+Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. To utilize the Parmys plugin, the ``-DYOSYS_PARMYS_PLUGIN=ON`` compile flag should be passed while building the VTR project with Yosys as a frontend.
 
 Detailed Command-line Options
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -312,4 +319,15 @@ Detailed Command-line Options
     UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions.
     The ``yosys-plugins`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
     It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
-    On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
+    On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
+
+.. option:: -mapper <PARSER>
+
+    Choose a partial mapper for the Yosys synthesizer [yosys (default), parmys (Partial Mapper for Yosys plugin)].
+    The Yosys default partial mapper will be used if no mapper is specified.
+
+    **Default:** yosys
+
+.. note::
+
+    Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available paramters see the `Parmys <https://github.com/CAS-Atlantic/parmys-plugin.git>`_ plugin page.

libs/EXTERNAL/CMakeLists.txt

@@ -100,6 +100,40 @@ if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
         ) 
     endif() 
 
+    if(${YOSYS_PARMYS_PLUGIN}) 
+        set(YOSYS_DATDIR ${libyosys_BINARY_DIR}/share/yosys) 
+        set(PARMYS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/parmys-plugin) 
+
+        ExternalProject_Add(parmys-plugin 
+            PREFIX "" 
+
+            GIT_REPOSITORY    https://github.com/CAS-Atlantic/parmys-plugin.git
+            GIT_TAG           v1.0
+            GIT_PROGRESS      TRUE 
+            
+            # setting source, build and install directories 
+            SOURCE_DIR "${PARMYS_SOURCE_DIR}" 
+            BUILD_IN_SOURCE TRUE 
+            INSTALL_DIR "" 
+
+            INSTALL_COMMAND "" 
+            CONFIGURE_COMMAND "" 
+            BUILD_COMMAND ${MAKE_PROGRAM} -C ${PARMYS_SOURCE_DIR} 
+                                        PATH=${libyosys_BINARY_DIR}/bin/:$ENV{PATH} 
+                                        install -j${CMAKE_BUILD_PARALLEL_LEVEL} 
+            
+            # redirect logs to a logfile
+            LOG_BUILD ON
+            LOG_UPDATE ON
+            LOG_INSTALL ON
+            LOG_CONFIGURE ON
+            LOG_OUTPUT_ON_FAILURE ON
+            
+            # dependency
+            DEPENDS yosys 
+        ) 
+    endif()
+
     # In addition to libyosys in the build folder, we copy the libyosys directory
     # into a temporary folder in the VTR root, named Yosys, to have access to Yosys 
     # (plugins) execs for using in VTR scripts (similar to VPR/vpr or ODIN_II/odin_II)
@@ -115,6 +149,9 @@ if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
     if(${YOSYS_SV_UHDM_PLUGIN})
         add_dependencies(vtr-yosys yosys-plugins)
     endif()
+    if(${YOSYS_PARMYS_PLUGIN})
+        add_dependencies(vtr-yosys parmys-plugin)
+    endif()
 
 endif()
 

vtr_flow/misc/yosyslib/synthesis_parmys.tcl

@@ -0,0 +1,81 @@
+yosys -import
+
+plugin -i parmys
+yosys -import
+
+read_verilog -nomem2reg +/parmys/vtr_primitives.v
+setattr -mod -set keep_hierarchy 1 single_port_ram
+setattr -mod -set keep_hierarchy 1 dual_port_ram
+
+puts "Using parmys as partial mapper"
+
+parmys_arch -a QQQ
+
+if {$env(PARSER) == "surelog" } {
+	puts "Using Yosys read_uhdm command"
+	plugin -i systemverilog
+	yosys -import
+	read_uhdm -debug XXX
+} elseif {$env(PARSER) == "yosys-plugin" } {
+	puts "Using Yosys read_systemverilog command"
+	plugin -i systemverilog
+	yosys -import
+	read_systemverilog -debug XXX
+} elseif {$env(PARSER) == "yosys" } {
+	puts "Using Yosys read_verilog command"
+	read_verilog -sv -nolatches XXX
+} else {
+	error "Invalid PARSER"
+}
+
+# Check that there are no combinational loops
+scc -select
+select -assert-none %
+select -clear
+
+hierarchy -check -auto-top -purge_lib
+
+opt_expr
+opt_clean
+check
+opt -nodffe -nosdff
+procs -norom
+fsm
+opt
+wreduce
+peepopt
+opt_clean
+share
+
+opt -full
+memory -nomap
+flatten
+
+opt -full
+
+techmap -map +/parmys/adff2dff.v
+techmap -map +/parmys/adffe2dff.v
+techmap -map +/parmys/aldff2dff.v
+techmap -map +/parmys/aldffe2dff.v
+
+opt -full
+
+#stat
+
+parmys -a QQQ -nopass -c odin_config.xml
+
+opt -full
+
+techmap 
+opt -fast
+
+dffunmap
+opt -fast -noff
+
+#autoname
+
+tee -o /dev/stdout stat
+
+hierarchy -check -auto-top -purge_lib
+
+write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

vtr_flow/scripts/python_libs/vtr/paths.py

@@ -21,6 +21,7 @@
 yosys_exe_path = yosys_path / "bin" / "yosys"
 yosys_lib_path = vtr_flow_path / "misc" / "yosyslib"
 yosys_script_path = yosys_lib_path / "synthesis.tcl"
+yosys_parmys_script_path = yosys_lib_path / "synthesis_parmys.tcl"
 
 # ARCHFPGA paths
 archfpga_path = root_path / "ArchFPGA"

vtr_flow/scripts/python_libs/vtr/yosys/yosys.py

@@ -5,6 +5,7 @@
 import shutil
 from collections import OrderedDict
 from pathlib import Path
+import xml.etree.ElementTree as ET
 import vtr
 
 # supported input file type by Yosys
@@ -31,6 +32,8 @@
 
 YOSYS_PARSERS = ["yosys", "surelog", "yosys-plugin"]
 
+YOSYS_MAPPERS = ["parmys", "yosys"]
+
 
 def create_circuits_list(main_circuit, include_files):
     """Create a list of supported HDL files"""
@@ -68,6 +71,7 @@ def init_script_file(
     memory_addr_width,
     min_hard_mult_size,
     min_hard_adder_size,
+    architecture_file_path,
 ):
     """initializing the raw yosys script file"""
     # specify the input files type
@@ -89,6 +93,7 @@ def init_script_file(
             "CCC": architecture_dsp_full_path,
             "TTT": str(vtr.paths.yosys_lib_path),
             "ZZZ": output_netlist,
+            "QQQ": architecture_file_path,
         },
     )
 
@@ -105,6 +110,58 @@ def init_script_file(
     vtr.file_replace(yosys_dpram_rename_full_path, {"PPP": memory_addr_width})
 
 
+# pylint: disable=too-many-arguments, too-many-locals
+def init_config_file(
+    odin_config_full_path,
+    circuit_list,
+    architecture_file,
+    output_netlist,
+    odin_parser_arg,
+    memory_addr_width,
+    min_hard_mult_size,
+    min_hard_adder_size,
+):
+    """initializing the raw odin config file"""
+    # specify the input files type
+    file_extension = os.path.splitext(circuit_list[0])[-1]
+    if file_extension not in FILE_TYPES:
+        raise vtr.VtrError("Inavlid input file type '{}'".format(file_extension))
+    input_file_type = FILE_TYPES[file_extension]
+
+    # Check if the user specifically requested for the UHDM parser
+    if odin_parser_arg == "-u":
+        input_file_type = "uhdm"
+
+    # Update the config file
+    vtr.file_replace(
+        odin_config_full_path,
+        {
+            "YYY": architecture_file,
+            "TTT": input_file_type,
+            "ZZZ": output_netlist,
+            "PPP": memory_addr_width,
+            "MMM": min_hard_mult_size,
+            "AAA": min_hard_adder_size,
+        },
+    )
+
+    # loading the given config file
+    config_file = ET.parse(odin_config_full_path)
+    root = config_file.getroot()
+
+    # based on the base config file
+    verilog_files_tag = root.find("inputs")
+    # remove the template line XXX, verilog_files_tag [1] is a comment
+    verilog_files_tag.remove(verilog_files_tag[1])
+    for circuit in circuit_list:
+        verilog_file = ET.SubElement(verilog_files_tag, "input_path_and_name")
+        verilog_file.tail = "\n\n\t" if (circuit == circuit_list[-1]) else "\n\n\t\t"
+        verilog_file.text = circuit
+
+    # update the config file with new values
+    config_file.write(odin_config_full_path)
+
+
 # pylint: disable=too-many-arguments, too-many-locals, too-many-statements, too-many-branches
 def run(
     architecture_file,
@@ -175,7 +232,10 @@ def run(
         yosys_exec = str(vtr.paths.yosys_exe_path)
 
     if yosys_script is None:
-        yosys_base_script = str(vtr.paths.yosys_script_path)
+        if yosys_args["mapper"] == "parmys":
+            yosys_base_script = str(vtr.paths.yosys_parmys_script_path)
+        else:
+            yosys_base_script = str(vtr.paths.yosys_script_path)
     else:
         yosys_base_script = str(Path(yosys_script).resolve())
 
@@ -210,6 +270,7 @@ def run(
 
     write_arch_bb_exec = str(vtr.paths.write_arch_bb_exe_path)
     architecture_dsp_full_path = str(vtr.paths.scripts_path / temp_dir / YOSYS_LIB_FILES["DSPBB"])
+    architecture_file_path = str(vtr.paths.scripts_path / architecture_file)
 
     # executing write_arch_bb to extract the black box definitions of the given arch file
     command_runner.run_system_command(
@@ -239,6 +300,25 @@ def run(
         vtr.determine_memory_addr_width(str(architecture_file)),
         min_hard_mult_size,
         min_hard_adder_size,
+        architecture_file_path,
+    )
+
+    odin_base_config = str(vtr.paths.odin_cfg_path)
+
+    # Copy the config file
+    odin_config = "odin_config.xml"
+    odin_config_full_path = str(temp_dir / odin_config)
+    shutil.copyfile(odin_base_config, odin_config_full_path)
+
+    init_config_file(
+        odin_config_full_path,
+        circuit_list,
+        architecture_file.name,
+        output_netlist.name,
+        None,
+        vtr.determine_memory_addr_width(str(architecture_file)),
+        min_hard_mult_size,
+        min_hard_adder_size,
     )
 
     # set the parser
@@ -252,6 +332,17 @@ def run(
             )
         )
 
+    # set the partial mapper
+    if yosys_args["mapper"] in YOSYS_MAPPERS:
+        os.environ["MAPPER"] = yosys_args["mapper"]
+        del yosys_args["mapper"]
+    else:
+        raise vtr.VtrError(
+            "Invalid partial mapper is specified for Yosys, available parsers are [{}]".format(
+                " ".join(str(x) for x in YOSYS_MAPPERS)
+            )
+        )
+
     cmd = [yosys_exec]
 
     for arg, value in yosys_args.items():

vtr_flow/scripts/run_vtr_flow.py

@@ -387,6 +387,12 @@ def vtr_command_argparser(prog=None):
         + "yosys-plugin (SystemVerilog)]. The script used the Yosys conventional Verilog"
         + " parser if this argument is not specified.",
     )
+    yosys.add_argument(
+        "-mapper",
+        default="yosys",
+        dest="mapper",
+        help="Choose the partial mapper fot VTR flow with Yosys frontend between [parmys, yosys].",
+    )
     #
     # VPR arguments
     #
@@ -733,6 +739,7 @@ def process_yosys_args(args):
     """
     yosys_args = OrderedDict()
     yosys_args["parser"] = args.parser
+    yosys_args["mapper"] = args.mapper
 
     return yosys_args
 

vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/koios/config/config.txt

@@ -0,0 +1,49 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog/koios
+
+# Path to directory of architectures to use
+archs_dir=arch/COFFE_22nm
+
+# Directory containing the verilog includes file(s)
+includes_dir=benchmarks/verilog/koios
+
+# Add circuits to list to sweep
+circuit_list_add=tpu_like.small.os.v
+circuit_list_add=tpu_like.small.ws.v
+circuit_list_add=dla_like.small.v
+circuit_list_add=bnn.v
+circuit_list_add=attention_layer.v
+circuit_list_add=conv_layer_hls.v
+circuit_list_add=conv_layer.v
+circuit_list_add=eltwise_layer.v
+circuit_list_add=robot_rl.v
+circuit_list_add=reduction_layer.v
+circuit_list_add=spmv.v
+circuit_list_add=softmax.v
+
+# Add architectures to list to sweep
+arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
+
+# Add include files to the list.
+# Some benchmarks instantiate hard dsp and memory blocks 
+# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
+# The hard_block_include.v file 
+# defines this macros, thereby enabling instantiations of the hard blocks
+include_list_add=hard_block_include.v
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 -start yosys -mapper parmys

vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/koios/config/golden_results.txt

@@ -0,0 +1,13 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  yosys_synth_time	  max_yosys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  tpu_like.small.os.v	  common	  1110.59	  vpr	  2.29 GiB	  	  -1	  -1	  19.63	  193924	  5	  146.86	  -1	  -1	  109788	  -1	  -1	  492	  355	  32	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  2406424	  355	  289	  25429	  18444	  2	  12323	  1433	  136	  136	  18496	  dsp_top	  auto	  213.9 MiB	  14.44	  352336	  2350.0 MiB	  33.86	  0.41	  5.56791	  -81804.5	  -5.56791	  2.1842	  11.33	  0.0355829	  0.0296736	  7.0167	  5.87884	  -1	  384672	  15	  5.92627e+08	  8.53857e+07	  4.08527e+08	  22087.3	  5.71	  8.53768	  7.19696	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  tpu_like.small.ws.v	  common	  1158.48	  vpr	  2.31 GiB	  	  -1	  -1	  25.68	  243200	  5	  117.53	  -1	  -1	  117100	  -1	  -1	  697	  357	  58	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  2420124	  357	  289	  25732	  20399	  2	  12732	  1667	  136	  136	  18496	  dsp_top	  auto	  237.3 MiB	  81.55	  219859	  2363.4 MiB	  36.29	  0.17	  8.94296	  -73584.4	  -8.94296	  2.88582	  12.32	  0.0201256	  0.0161994	  5.28974	  4.16286	  -1	  286898	  15	  5.92627e+08	  9.4939e+07	  4.08527e+08	  22087.3	  4.27	  6.36971	  5.09181	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  dla_like.small.v	  common	  3579.55	  vpr	  1.78 GiB	  	  -1	  -1	  92.70	  736444	  6	  1349.76	  -1	  -1	  389852	  -1	  -1	  3859	  206	  132	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  1864068	  206	  13	  165036	  139551	  1	  69347	  4322	  88	  88	  7744	  dsp_top	  auto	  1066.9 MiB	  1806.28	  606504	  1620.8 MiB	  111.75	  0.90	  5.05712	  -150965	  -5.05712	  5.05712	  2.15	  0.0366279	  0.0287263	  5.24481	  3.9573	  -1	  879743	  16	  2.4541e+08	  1.54276e+08	  1.69370e+08	  21871.2	  10.28	  7.22839	  5.55706	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  bnn.v	  common	  1151.22	  vpr	  2.04 GiB	  	  -1	  -1	  75.26	  728748	  3	  74.57	  -1	  -1	  412708	  -1	  -1	  6192	  260	  0	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  2141884	  260	  122	  206251	  154342	  1	  87289	  6637	  87	  87	  7569	  clb	  auto	  1314.5 MiB	  226.59	  923276	  1734.9 MiB	  370.39	  2.59	  6.83078	  -142705	  -6.83078	  6.83078	  3.93	  0.327259	  0.305731	  36.0045	  30.6725	  -1	  1211227	  18	  2.37162e+08	  1.8877e+08	  1.65965e+08	  21927.0	  33.60	  46.6811	  39.6048	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  attention_layer.v	  common	  1049.49	  vpr	  1007.30 MiB	  	  -1	  -1	  31.68	  319060	  5	  16.80	  -1	  -1	  134876	  -1	  -1	  998	  1052	  194	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  1031476	  1052	  32	  45971	  36479	  1	  23767	  2374	  82	  82	  6724	  dsp_top	  auto	  316.0 MiB	  604.19	  257027	  1007.3 MiB	  68.40	  0.50	  5.72825	  -88186.6	  -5.72825	  5.72825	  3.50	  0.10262	  0.0674806	  15.6345	  12.2949	  -1	  397496	  16	  2.09174e+08	  7.94267e+07	  1.47429e+08	  21925.8	  12.26	  19.34	  15.3468	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  conv_layer_hls.v	  common	  526.10	  vpr	  1.34 GiB	  	  -1	  -1	  16.38	  267080	  3	  16.19	  -1	  -1	  56524	  -1	  -1	  1734	  1016	  21	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  1410004	  1016	  2244	  12831	  14373	  1	  7151	  5027	  104	  104	  10816	  io	  auto	  141.0 MiB	  75.70	  69573	  1377.0 MiB	  32.21	  0.22	  4.64445	  -17031.1	  -4.64445	  4.64445	  7.07	  0.057679	  0.0547243	  7.10767	  6.66414	  -1	  95151	  13	  3.44415e+08	  5.43223e+07	  2.37404e+08	  21949.3	  2.81	  8.56776	  8.02199	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  conv_layer.v	  common	  297.35	  vpr	  545.57 MiB	  	  -1	  -1	  13.12	  147948	  4	  116.75	  -1	  -1	  82672	  -1	  -1	  819	  91	  56	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  558664	  91	  65	  33169	  28056	  2	  12823	  1073	  56	  56	  3136	  dsp_top	  auto	  250.4 MiB	  16.70	  171184	  545.6 MiB	  20.48	  0.17	  4.53047	  -55396.1	  -4.53047	  1.87418	  1.27	  0.0582637	  0.0532144	  6.28727	  5.31139	  -1	  242052	  13	  9.76016e+07	  4.12216e+07	  6.79229e+07	  21659.1	  5.73	  8.34868	  7.09197	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  eltwise_layer.v	  common	  140.72	  vpr	  475.44 MiB	  	  -1	  -1	  5.09	  84496	  4	  8.49	  -1	  -1	  57108	  -1	  -1	  353	  152	  72	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  486848	  152	  97	  14485	  12275	  2	  7010	  721	  56	  56	  3136	  dsp_top	  auto	  142.7 MiB	  10.46	  130410	  475.4 MiB	  11.69	  0.11	  3.6181	  -22623.8	  -3.6181	  1.61706	  1.34	  0.058637	  0.0557739	  4.83872	  4.10451	  -1	  192506	  16	  9.76016e+07	  3.16899e+07	  6.79229e+07	  21659.1	  4.41	  6.2521	  5.37969	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  robot_rl.v	  common	  173.65	  vpr	  473.83 MiB	  	  -1	  -1	  15.89	  244148	  5	  12.11	  -1	  -1	  76952	  -1	  -1	  874	  3	  84	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  485204	  3	  384	  24598	  22966	  1	  12278	  1363	  52	  52	  2704	  memory	  auto	  221.4 MiB	  18.52	  106556	  473.8 MiB	  21.55	  0.17	  5.86275	  -35817.1	  -5.86275	  5.86275	  0.88	  0.0376993	  0.0159897	  4.7203	  3.73943	  -1	  173563	  16	  8.30642e+07	  4.05203e+07	  5.85728e+07	  21661.5	  5.12	  6.87595	  5.43564	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  reduction_layer.v	  common	  120.60	  vpr	  320.91 MiB	  	  -1	  -1	  14.38	  304872	  6	  13.37	  -1	  -1	  73360	  -1	  -1	  644	  37	  52	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  328612	  37	  17	  16436	  14191	  1	  8814	  750	  38	  38	  1444	  memory	  auto	  171.2 MiB	  20.07	  98868	  306.5 MiB	  15.40	  0.19	  5.67358	  -37046.8	  -5.67358	  5.67358	  0.44	  0.037453	  0.0308559	  2.62088	  2.04348	  -1	  162626	  16	  4.31434e+07	  2.51293e+07	  3.09543e+07	  21436.5	  4.48	  4.28838	  3.4871	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  spmv.v	  common	  326.85	  vpr	  944.12 MiB	  	  -1	  -1	  7.94	  190760	  6	  21.93	  -1	  -1	  69896	  -1	  -1	  648	  82	  232	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  966776	  82	  17	  16299	  14395	  1	  9060	  1011	  84	  84	  7056	  memory	  auto	  159.0 MiB	  19.50	  170039	  944.1 MiB	  9.84	  0.12	  4.90582	  -40189.1	  -4.90582	  4.90582	  3.31	  0.0593175	  0.0558204	  3.35984	  2.70486	  -1	  229056	  13	  2.2198e+08	  5.81417e+07	  1.54484e+08	  21894.0	  4.48	  4.48777	  3.62589	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  softmax.v	  common	  163.15	  vpr	  442.01 MiB	  	  -1	  -1	  12.69	  291904	  10	  14.29	  -1	  -1	  57864	  -1	  -1	  516	  402	  0	  -1	  success	  v8.0.0-6743-g5889a1dfb-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-53-generic x86_64	  2022-12-06T13:04:10	  casa48	  /home/casa/Desktop/CAS-Atlantic/vtr_yosys_parmys_23	  452616	  402	  150	  12975	  11797	  1	  7825	  1105	  54	  54	  2916	  dsp_top	  auto	  134.4 MiB	  22.32	  78842	  442.0 MiB	  12.47	  0.13	  7.87576	  -13078	  -7.87576	  7.87576	  0.88	  0.0504971	  0.0489573	  3.59855	  3.21012	  -1	  128692	  16	  8.95105e+07	  2.37886e+07	  6.32721e+07	  21698.2	  3.25	  5.00922	  4.47104	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 

vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/task_list.txt

@@ -0,0 +1,2 @@
+regression_tests/vtr_reg_yosys_parmys/vtr_benchmarks/
+regression_tests/vtr_reg_yosys_parmys/koios/

vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/vtr_benchmarks/config/config.txt

@@ -0,0 +1,48 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=arm_core.v
+circuit_list_add=bgm.v
+circuit_list_add=blob_merge.v
+circuit_list_add=boundtop.v
+circuit_list_add=ch_intrinsics.v
+circuit_list_add=diffeq1.v
+circuit_list_add=diffeq2.v
+circuit_list_add=mkDelayWorker32B.v
+circuit_list_add=mkPktMerge.v
+circuit_list_add=mkSMAdapter4B.v
+circuit_list_add=or1200.v
+circuit_list_add=raygentop.v
+circuit_list_add=sha.v
+circuit_list_add=spree.v
+circuit_list_add=stereovision0.v
+circuit_list_add=stereovision1.v
+circuit_list_add=stereovision2.v
+circuit_list_add=stereovision3.v
+circuit_list_add=LU8PEEng.v
+circuit_list_add=LU32PEEng.v
+circuit_list_add=mcml.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -crit_path_router_iterations 100 -start yosys -mapper parmys