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Adding a reg test called strong_fix_clusters to vtr_reg_strong to test functionality of fix_clusters option
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‎vtr_flow/arch/reg_test_archs/Readme.txt

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###################################################
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# Architecture Files
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###################################################
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This directory contains architecture files that are used in regression testing.
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‎vtr_flow/arch/reg_test_archs/fix_clusters_test_arch.xml

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<!--
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Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
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- 40 nm technology
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- General purpose logic block:
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K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
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with optionally registered outputs
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch)
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that describe them.
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-->
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<models>
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</models>
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<tiles>
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<tile name="io" area="0">
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<sub_tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io" pin_mapping="direct"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb" area="53894">
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<sub_tile name="clb" capacity="6">
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<equivalent_sites>
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<site pb_type="clb" pin_mapping="direct"/>
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</equivalent_sites>
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout>
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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</layout>
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<device>
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<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
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models. We are modifying the delay values however, to include metal C and R, which allows more architecture
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experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
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(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
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45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
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RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
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lined up with Stratix IV.
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We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
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Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
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by 2.5x when looking up in Jeff's tables.
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The delay values are lined up with Stratix IV, which has an architecture similar to this
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proposed FPGA, and which is also 40 nm
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C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
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4x minimum drive strength buffer. -->
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
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area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
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-->
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
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book area formula. This means the mux transistors are about 5x minimum drive strength.
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We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
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mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
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the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
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by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
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buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
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I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
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(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
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The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
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2.5x when looking up in Jeff's tables.
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Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
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This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
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With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
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reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
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<segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<!-- Define I/O pads begin -->
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
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<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs.
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Delays below come from Ian Kuon. They are small, so they should be interpreted as
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the delays to and from registers in the I/O (and generally I/Os are registered
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today and that is when you timing analyze them.
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-->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<!-- Place I/Os on the sides of the FPGA -->
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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<!-- Define general purpose logic block (CLB) begin -->
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<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
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area is 60 L^2 yields a tile area of 84375 MWTAs.
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Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
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This means that only 37% of our area is in the general routing, and 63% is inside the logic
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block. Note that the crossbar / local interconnect is considered part of the logic block
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area in this analysis. That is a lower proportion of of routing area than most academics
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assume, but note that the total routing area really includes the crossbar, which would push
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routing area up significantly, we estimate into the ~70% range.
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-->
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe fracturable logic element.
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Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
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The outputs of the fracturable logic element can be optionally registered
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-->
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<!-- Dual 5-LUT mode definition begin -->
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<mode name="n2_lut5">
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<pb_type name="lut5inter" num_pb="1">
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<input name="in" num_pins="5"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="ble5" num_pb="2">
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<input name="in" num_pins="5"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define the LUT -->
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<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="5" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
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we instead take the average of these numbers to get more stable results
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82e-12
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173e-12
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261e-12
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263e-12
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398e-12
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-->
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<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
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235e-12
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235e-12
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235e-12
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235e-12
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235e-12
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</delay_matrix>
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</pb_type>
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<!-- Define the flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
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<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
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</direct>
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<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
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<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
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<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
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<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
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<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
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<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
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<direct name="direct2" input="lut5inter.out" output="fle.out"/>
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<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
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</interconnect>
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</mode>
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<!-- Dual 5-LUT mode definition end -->
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<!-- 6-LUT mode definition begin -->
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<mode name="n1_lut6">
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<!-- Define 6-LUT mode -->
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
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we instead take the average of these numbers to get more stable results
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82e-12
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173e-12
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261e-12
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263e-12
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398e-12
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397e-12
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-->
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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<direct name="direct2" input="lut6.out" output="ff.D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble6.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble6.in"/>
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<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble6.clk"/>
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</interconnect>
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</mode>
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<!-- 6-LUT mode definition end -->
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</pb_type>
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<interconnect>
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<!-- We use a full crossbar to get logical equivalence at inputs of CLB
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The delays below come from Stratix IV. the delay through a connection block
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input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
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delay on the connection block input mux (modeled by Ian Kuon), so the remaining
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delay within the crossbar is 95 ps.
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The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
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Since all our outputs LUT outputs go to a BLE output, and have a delay of
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25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
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to get the part that should be marked on the crossbar. -->
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<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
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By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
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then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
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naive specification).
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-->
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<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
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<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
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</interconnect>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<!-- Place this general purpose logic block in any unspecified column -->
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</pb_type>
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<!-- Define general purpose logic block (CLB) ends -->
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</complexblocklist>
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<power>
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<local_interconnect C_wire="2.5e-10"/>
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<mux_transistor_size mux_transistor_size="3"/>
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<FF_size FF_size="4"/>
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<LUT_transistor_size LUT_transistor_size="4"/>
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</power>
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<clocks>
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<clock buffer_size="auto" C_wire="2.5e-10"/>
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</clocks>
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</architecture>

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