File tree 5 files changed +6
-6
lines changed
vtr_flow/tasks/regression_tests/vtr_reg_strong
strong_blocks_with_no_inputs/config
strong_clock_modeling/config
strong_global_nonuniform/config 5 files changed +6
-6
lines changed Original file line number Diff line number Diff line change @@ -25,7 +25,7 @@ parse_file=vpr_standard.txt
2525qor_parse_file=qor_standard.txt
2626
2727# Pass requirements
28- pass_requirements_file=pass_requirements .txt
28+ pass_requirements_file=pass_requirements_small .txt
2929
3030# Script parameters
3131script_params_common = -track_memory_usage
Original file line number Diff line number Diff line change 11 arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets
22 timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.28 vpr 56.10 MiB -1 -1 0.05 20076 1 0.00 -1 -1 32876 -1 -1 1 2 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 57444 2 1 3 4 1 3 4 3 3 9 -1 auto 17.5 MiB 0.00 4 56.1 MiB 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 0.00 7.472e-06 4.444e-06 5.2255e-05 3.5357e-05 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.000150639 0.000101445 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2
33 timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.26 vpr 56.07 MiB -1 -1 0.05 20348 1 0.00 -1 -1 33116 -1 -1 1 2 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 57412 2 1 3 4 1 3 4 3 3 9 -1 auto 17.5 MiB 0.00 6 56.1 MiB 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 0.00 7.373e-06 4.228e-06 5.4128e-05 3.6541e-05 -1 8 3 53894 53894 14028.3 1558.70 0.00 0.000159415 0.000108151 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3
4- timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 20.62 yosys 204.34 MiB -1 -1 16.70 209240 2 1.15 -1 -1 59832 -1 -1 155 5 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 59280 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.02 22 57.9 MiB 0.07 0.00 1.10153 -11.3996 -1.10153 1.10153 0.01 0.000146864 0.000131212 0.011265 0.0101019 -1 34 5 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0144781 0.0131086 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9
4+ timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 20.62 yosys 204.34 MiB -1 -1 16.70 209240 2 1.15 -1 -1 59832 -1 -1 155 5 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 59280 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.02 22 57.9 MiB 0.07 0.00 1.10153 -11.3996 -1.10153 1.10153 0.01 0.000146864 0.000131212 0.011265 0.0101019 -1 38 5 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0144781 0.0131086 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9
55 timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 20.82 yosys 204.26 MiB -1 -1 16.55 209160 2 1.15 -1 -1 59996 -1 -1 155 5 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 59440 5 156 191 347 1 163 316 15 15 225 clb auto 19.8 MiB 0.02 25 58.0 MiB 0.08 0.00 1.12309 -11.8205 -1.12309 1.12309 0.01 0.000159954 0.000141912 0.0122901 0.011012 -1 48 4 9.10809e+06 8.35357e+06 858153. 3814.01 0.00 0.0153796 0.0139115 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10
66 timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.34 vpr 60.93 MiB -1 -1 0.06 20324 1 0.00 -1 -1 33212 -1 -1 1 2 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 62388 2 1 3 4 1 3 4 3 3 9 -1 auto 22.2 MiB 0.00 4 60.9 MiB 0.01 0.00 0.571526 -0.946421 -0.571526 0.571526 0.00 2.0228e-05 1.4173e-05 7.1706e-05 4.9857e-05 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.000190797 0.00013594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2
77 timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 61.09 MiB -1 -1 0.06 20372 1 0.01 -1 -1 33044 -1 -1 1 2 0 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 62556 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.00 6 61.1 MiB 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 0.00 7.855e-06 4.642e-06 5.7063e-05 3.8267e-05 -1 8 3 53894 53894 14028.3 1558.70 0.00 0.000173245 0.000119981 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3
Original file line number Diff line number Diff line change @@ -21,7 +21,7 @@ parse_file=vpr_standard.txt
2121qor_parse_file=qor_standard.txt
2222
2323# Pass requirements
24- pass_requirements_file=pass_requirements .txt
24+ pass_requirements_file=pass_requirements_small .txt
2525
2626# Script parameters
2727script_params =
Original file line number Diff line number Diff line change @@ -26,7 +26,7 @@ parse_file=vpr_standard.txt
2626qor_parse_file=qor_standard.txt
2727
2828# Pass requirements
29- pass_requirements_file=pass_requirements .txt
29+ pass_requirements_file=pass_requirements_small .txt
3030
3131# Script parameters
3232script_params = --route_type global --seed 2
Original file line number Diff line number Diff line change 11arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack
2- k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.31564 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.31564 -1 1.07053 -1 1.76203 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.16427 -1 3.30853 -1 -1.48434 -1 -1 -1 -1
3- k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.31564 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.31564 -1 1.07053 -1 1.76203 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.16427 -1 3.30853 -1 -1.48434 -1 -1 -1 -1
2+ k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.44 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.44 -1 1.07053 -1 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.5 -1 3.30853 -1 -1.85 -1 -1 -1 -1
3+ k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.44 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.44 -1 1.07053 -1 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.5 -1 3.30853 -1 -1.85 -1 -1 -1 -1
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