File tree 14 files changed +87
-87
lines changed
vtr_flow/tasks/regression_tests
strong_cin_tie_off/config
strong_clock_aliases_set_delay/config
strong_fracturable_luts/config
strong_post_routing_sync/config
strong_cin_tie_off/config
strong_clock_aliases_set_delay/config
strong_fix_pins_random/config
strong_global_nonuniform/config
strong_post_routing_sync/config
strong_soft_multipliers/config
14 files changed +87
-87
lines changed Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
2- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.93 vpr 65.66 MiB -1 -1 0.06 20352 1 0.01 -1 -1 35860 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8 .0-1014 -azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67236 9 8 75 70 1 34 20 5 5 25 clb auto 27.3 MiB 0.38 91 452 103 339 10 65.7 MiB 0.00 0.00 2.64007 -28.7664 -2.64007 2.64007 0.02 7.4568e-05 6.6193e-05 0.00195079 0.00178739 38 154 16 151211 75605.7 48493.3 1939.73 0.11 0.0243483 0.0205304 2100 8065 -1 119 18 114 142 4814 2350 2.64007 2.64007 -31.8474 -2.64007 0 0 61632.8 2465.31 0.01 0.01 0.01 -1 -1 0.01 0.00485388 0.00446806 13 18 -1 -1 -1 -1
3- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.87 vpr 66.77 MiB -1 -1 0.08 20736 1 0.01 -1 -1 35944 -1 -1 7 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8 .0-1014 -azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68372 19 18 308 249 1 142 44 6 6 36 clb auto 28.4 MiB 2.88 521 2662 840 1802 20 66.8 MiB 0.02 0.00 4.88121 -98.944 -4.88121 4.88121 0.04 0.000207626 0.000184303 0.0103914 0.00951356 54 1083 35 403230 176413 113905 . 3164.04 0.39 0.0844877 0.0734258 4050 20995 -1 745 17 630 985 35752 13957 5.5504 5.5504 -118.789 -5.5504 0 0 146644 . 4073.44 0.01 0.02 0.01 -1 -1 0.01 0.014306 0.0132257 55 83 -1 -1 -1 -1
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
2+ k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.40 vpr 64.12 MiB -1 -1 0.11 20096 1 0.02 -1 -1 36000 -1 -1 3 9 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5 .0-1025 -azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65664 9 8 75 70 1 34 20 5 5 25 clb auto 25.6 MiB 0.60 97 74 18 56 0 64.1 MiB 0.00 0.00 2.64007 -29.44 -2.64007 2.64007 0.03 0.000119511 0.000105355 0.00150744 0.00144146 -1 -1 -1 -1 20 183 15 151211 75605.7 29112.5 1164.50 0.11 0.0175261 0.0154045 1812 4729 -1 161 15 134 153 5442 3071 2.98537 2.98537 -38.4554 -2.98537 0 0 37105.9 1484.24 0.00 0.01 0.01 -1 -1 0.00 0.00675063 0.00621765 13 18 -1 -1 -1 -1
3+ k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.11 vpr 65.06 MiB -1 -1 0.13 20864 1 0.02 -1 -1 36332 -1 -1 7 19 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5 .0-1025 -azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66624 19 18 308 249 1 142 44 6 6 36 clb auto 26.7 MiB 4.50 509 2277 492 1758 27 65.1 MiB 0.04 0.00 4.8135 -98.9875 -4.8135 4.8135 0.06 0.000372692 0.000330895 0.0147327 0.0133843 -1 -1 -1 -1 60 910 23 403230 176413 127342 . 3537.27 0.64 0.156558 0.137174 4190 22875 -1 726 16 651 1079 37320 14467 4.73636 4.73636 -105.338 -4.73636 0 0 157803 . 4383.41 0.02 0.03 0.02 -1 -1 0.02 0.0215368 0.0200712 55 83 -1 -1 -1 -1
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.30 vpr 57.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/ vtr-verilog-to-routing/vtr-verilog-to-routing 59208 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.01 4 15 2 10 3 57.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 4.3769e -05 3.8064e -05 0.000324999 0.000293005 4 6 2 72000 36000 2827.54 176.721 0.01 0.00228834 0.0020767 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.00 0.00 0.00 -1 -1 0.00 0.00162095 0.00152882
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.20 vpr 57.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 59180 2 2 22 24 2 4 6 4 4 16 clb auto 19.4 MiB 0.01 8 15 5 8 2 57.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 4.865e -05 4.0365e -05 0.000331746 0.000291111 -1 -1 -1 -1 6 13 3 72000 36000 4025.56 251.598 0.01 0.00265857 0.00243025 660 1032 -1 12 5 7 7 429 325 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00194089 0.00183475
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
2- k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.02 vpr 64.76 MiB -1 -1 0.23 21996 3 0.05 -1 -1 36460 -1 -1 67 99 1 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3 .0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic /vtr-verilog-to-routing 66316 99 130 343 473 1 217 297 13 13 169 clb auto 26.2 MiB 0.86 456 64.8 MiB 0.12 0.00 34 1050 8 0 0 460544 . 2725.11 0.60
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
2+ k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.53 vpr 66.66 MiB -1 -1 0.36 21504 3 0.08 -1 -1 41652 -1 -1 66 99 1 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing /vtr-verilog-to-routing 68264 99 130 344 474 1 218 296 13 13 169 clb auto 27.6 MiB 1.16 826 30862 5429 11872 13561 66.7 MiB 0.05 0.00 28 1633 9 0 0 403031 . 2384.80 1.91
Original file line number Diff line number Diff line change 11 arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack
2- k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1
3- k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1
2+ k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1
3+ k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1
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