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resolved conflicts with master branch
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‎.github/workflows/test.yml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,11 @@ jobs:
141141
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
142142
suite: 'vtr_reg_basic'
143143
},
144+
{
145+
name: 'Basic with highest assertion level',
146+
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
147+
suite: 'vtr_reg_basic'
148+
},
144149
{
145150
name: 'Basic_odin',
146151
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',

‎.gitignore

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,7 @@ tags
144144
#
145145
.vscode
146146
.history
147+
.cache
147148
#eclipse project
148149
.project
149150

@@ -153,4 +154,4 @@ tags
153154
.idea
154155
cmake-build-debug
155156
cmake-build-release
156-
/.metadata/
157+
/.metadata/

‎doc/src/api/vpr/rr_graph.rst

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ RRGraphView
77

88
.. doxygenfile:: rr_graph_view.h
99
:project: librrgraph
10-
:sections: detaileddescription
10+
:sections: briefdescription detaileddescription func prototype user-defined public-func
1111

1212
.. doxygenclass:: RRGraphView
1313
:project: librrgraph
@@ -18,7 +18,7 @@ RRGraphBuilder
1818

1919
.. doxygenfile:: rr_graph_builder.h
2020
:project: librrgraph
21-
:sections: detaileddescription
21+
:sections: briefdescription detaileddescription func prototype user-defined public-func
2222

2323
.. doxygenclass:: RRGraphBuilder
2424
:project: librrgraph
@@ -29,7 +29,7 @@ RRSpatialLookup
2929

3030
.. doxygenfile:: rr_spatial_lookup.h
3131
:project: librrgraph
32-
:sections: detaileddescription
32+
:sections: briefdescription detaileddescription func prototype user-defined public-func
3333

3434
.. doxygenclass:: RRSpatialLookup
3535
:project: librrgraph

‎doc/src/arch/reference.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,8 @@ The valid tags within the ``<layout>`` tag are:
158158

159159
.. note:: At most one ``<auto_layout>`` can be specified.
160160

161+
.. _fixed_arch_grid_layout:
162+
161163
.. arch:tag:: <fixed_layout name="string" width="int" height="int">
162164
163165
:req_param name:

‎doc/src/vpr/command_line_usage.rst

Lines changed: 28 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,23 @@ VPR runs all stages of (pack, place, route, and analysis) if none of :option:`--
8282

8383
**Default:** ``off``
8484

85+
.. option:: --analytical_place
86+
87+
Run the analytical placement flow.
88+
This flows uses an integrated packing and placement algorithm which uses information from the primitive level to improve clustering and placement;
89+
as such, the :option:`--pack` and :option:`--place` options should not be set when this option is set.
90+
This flow requires that the device has a fixed size and some of the primitive blocks are fixed somewhere on the device grid.
91+
92+
.. seealso:: See :ref:`Fixed FPGA Grid Layout <fixed_arch_grid_layout>` and :option:`--device` for how to fix the device size.
93+
94+
.. seealso:: See :ref:`VPR Placement Constraints <placement_constraints>` for how to fix primitive blocks in a design to the device grid.
95+
96+
.. warning::
97+
98+
This analytical placement flow is experimental and under active development.
99+
100+
**Default:** ``off``
101+
85102
.. option:: --route
86103

87104
Run routing stage
@@ -979,15 +996,16 @@ The following options are only valid when the placement engine is in timing-driv
979996

980997
**Default:** ``8.0``
981998

982-
.. option:: --place_delay_model {delta, delta_override}
999+
.. option:: --place_delay_model {simple, delta, delta_override}
9831000

9841001
Controls how the timing-driven placer estimates delays.
9851002

986-
* ``delta`` The router is used to profile delay from various locations in the grid for various differences in position
1003+
* ``simple`` The placement delay estimator is built from the router lookahead. This takes less CPU time to build and it and still as accurate as the ``delta` model.
1004+
* ``delta`` The router is used to profile delay from various locations in the grid for various differences in position.
9871005
* ``delta_override`` Like ``delta`` but also includes special overrides to ensure effects of direct connects between blocks are accounted for.
9881006
This is potentially more accurate but is more complex and depending on the architecture (e.g. number of direct connects) may increase place run-time.
9891007

990-
**Default:** ``delta``
1008+
**Default:** ``simple``
9911009

9921010
.. option:: --place_delay_model_reducer {min, max, median, arithmean, geomean}
9931011

@@ -1292,6 +1310,13 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout
12921310
* `swns` - setup Worst Negative Slack (sWNS) [ns]
12931311
* `stns` - Setup Total Negative Slack (sTNS) [ns]
12941312

1313+
.. option:: --route_verbosity <int>
1314+
1315+
Controls the verbosity of routing output.
1316+
High values produce more detailed output, which can be useful for debugging or understanding the routing process.
1317+
1318+
**Default**: ``1``
1319+
12951320
.. _timing_driven_router_options:
12961321

12971322
Timing-Driven Router Options

‎libs/EXTERNAL/libcatch2

Submodule libcatch2 updated 86 files

‎libs/libarchfpga/src/parse_switchblocks.cpp

Lines changed: 71 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,9 @@ static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire
6565
/* Parses the number of connections type */
6666
static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
6767

68+
/* Set connection from_side and to_side for custom switch block pattern*/
69+
static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type);
70+
6871
/* parse switch_override in wireconn */
6972
static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches);
7073

@@ -269,6 +272,70 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn) {
269272
wireconn.num_conns_formula = num_conns;
270273
}
271274

275+
//set sides for a specific conn for custom switch block pattern
276+
static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type) {
277+
if (0 == strcmp(func_type, "lt")) {
278+
conn.set_sides(LEFT, TOP);
279+
} else if (0 == strcmp(func_type, "lr")) {
280+
conn.set_sides(LEFT, RIGHT);
281+
} else if (0 == strcmp(func_type, "lb")) {
282+
conn.set_sides(LEFT, BOTTOM);
283+
} else if (0 == strcmp(func_type, "la")) {
284+
conn.set_sides(LEFT, ABOVE);
285+
} else if (0 == strcmp(func_type, "lu")) {
286+
conn.set_sides(LEFT, UNDER);
287+
} else if (0 == strcmp(func_type, "tl")) {
288+
conn.set_sides(TOP, LEFT);
289+
} else if (0 == strcmp(func_type, "tb")) {
290+
conn.set_sides(TOP, BOTTOM);
291+
} else if (0 == strcmp(func_type, "tr")) {
292+
conn.set_sides(TOP, RIGHT);
293+
} else if (0 == strcmp(func_type, "ta")) {
294+
conn.set_sides(TOP, ABOVE);
295+
} else if (0 == strcmp(func_type, "tu")) {
296+
conn.set_sides(TOP, UNDER);
297+
} else if (0 == strcmp(func_type, "rt")) {
298+
conn.set_sides(RIGHT, TOP);
299+
} else if (0 == strcmp(func_type, "rl")) {
300+
conn.set_sides(RIGHT, LEFT);
301+
} else if (0 == strcmp(func_type, "rb")) {
302+
conn.set_sides(RIGHT, BOTTOM);
303+
} else if (0 == strcmp(func_type, "ra")) {
304+
conn.set_sides(RIGHT, ABOVE);
305+
} else if (0 == strcmp(func_type, "ru")) {
306+
conn.set_sides(RIGHT, UNDER);
307+
} else if (0 == strcmp(func_type, "bl")) {
308+
conn.set_sides(BOTTOM, LEFT);
309+
} else if (0 == strcmp(func_type, "bt")) {
310+
conn.set_sides(BOTTOM, TOP);
311+
} else if (0 == strcmp(func_type, "br")) {
312+
conn.set_sides(BOTTOM, RIGHT);
313+
} else if (0 == strcmp(func_type, "ba")) {
314+
conn.set_sides(BOTTOM, ABOVE);
315+
} else if (0 == strcmp(func_type, "bu")) {
316+
conn.set_sides(BOTTOM, UNDER);
317+
} else if (0 == strcmp(func_type, "al")) {
318+
conn.set_sides(ABOVE, LEFT);
319+
} else if (0 == strcmp(func_type, "at")) {
320+
conn.set_sides(ABOVE, TOP);
321+
} else if (0 == strcmp(func_type, "ar")) {
322+
conn.set_sides(ABOVE, RIGHT);
323+
} else if (0 == strcmp(func_type, "ab")) {
324+
conn.set_sides(ABOVE, BOTTOM);
325+
} else if (0 == strcmp(func_type, "ul")) {
326+
conn.set_sides(UNDER, LEFT);
327+
} else if (0 == strcmp(func_type, "ut")) {
328+
conn.set_sides(UNDER, TOP);
329+
} else if (0 == strcmp(func_type, "ur")) {
330+
conn.set_sides(UNDER, RIGHT);
331+
} else if (0 == strcmp(func_type, "ub")) {
332+
conn.set_sides(UNDER, BOTTOM);
333+
} else {
334+
/* unknown permutation function */
335+
archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
336+
}
337+
}
338+
272339
/* Loads permutation funcs specified under Node into t_switchblock_inf. Node should be
273340
* <switchfuncs> */
274341
void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
@@ -300,34 +367,8 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu
300367
func_formula = get_attribute(SubElem, "formula", loc_data).as_string(nullptr);
301368

302369
/* go through all the possible cases of func_type */
303-
if (0 == strcmp(func_type, "lt")) {
304-
conn.set_sides(LEFT, TOP);
305-
} else if (0 == strcmp(func_type, "lr")) {
306-
conn.set_sides(LEFT, RIGHT);
307-
} else if (0 == strcmp(func_type, "lb")) {
308-
conn.set_sides(LEFT, BOTTOM);
309-
} else if (0 == strcmp(func_type, "tl")) {
310-
conn.set_sides(TOP, LEFT);
311-
} else if (0 == strcmp(func_type, "tb")) {
312-
conn.set_sides(TOP, BOTTOM);
313-
} else if (0 == strcmp(func_type, "tr")) {
314-
conn.set_sides(TOP, RIGHT);
315-
} else if (0 == strcmp(func_type, "rt")) {
316-
conn.set_sides(RIGHT, TOP);
317-
} else if (0 == strcmp(func_type, "rl")) {
318-
conn.set_sides(RIGHT, LEFT);
319-
} else if (0 == strcmp(func_type, "rb")) {
320-
conn.set_sides(RIGHT, BOTTOM);
321-
} else if (0 == strcmp(func_type, "bl")) {
322-
conn.set_sides(BOTTOM, LEFT);
323-
} else if (0 == strcmp(func_type, "bt")) {
324-
conn.set_sides(BOTTOM, TOP);
325-
} else if (0 == strcmp(func_type, "br")) {
326-
conn.set_sides(BOTTOM, RIGHT);
327-
} else {
328-
/* unknown permutation function */
329-
archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
330-
}
370+
set_switch_func_type(conn, func_type);
371+
331372
func_ptr = &(sb->permutation_map[conn]);
332373

333374
/* Here we load the specified switch function(s) */
@@ -404,8 +445,8 @@ static void check_bidir_switchblock(const t_permutation_map* permutation_map) {
404445
SB_Side_Connection conn;
405446

406447
/* iterate over all combinations of from_side -> to side */
407-
for (e_side from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
408-
for (e_side to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
448+
for (e_side from_side : TOTAL_2D_SIDES) {
449+
for (e_side to_side : TOTAL_2D_SIDES) {
409450
/* can't connect a switchblock side to itself */
410451
if (from_side == to_side) {
411452
continue;

‎libs/libarchfpga/src/physical_types.h

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -176,10 +176,17 @@ enum e_side : unsigned char {
176176
RIGHT = 1,
177177
BOTTOM = 2,
178178
LEFT = 3,
179-
NUM_SIDES
179+
NUM_2D_SIDES = 4,
180+
ABOVE = 5,
181+
UNDER = 7,
182+
NUM_3D_SIDES = 6,
180183
};
181-
constexpr std::array<e_side, NUM_SIDES> SIDES = {{TOP, RIGHT, BOTTOM, LEFT}}; //Set of all side orientations
182-
constexpr std::array<const char*, NUM_SIDES> SIDE_STRING = {{"TOP", "RIGHT", "BOTTOM", "LEFT"}}; //String versions of side orientations
184+
185+
constexpr std::array<e_side, NUM_2D_SIDES> TOTAL_2D_SIDES = {{TOP, RIGHT, BOTTOM, LEFT}}; //Set of all side orientations
186+
constexpr std::array<const char*, NUM_2D_SIDES> TOTAL_2D_SIDE_STRINGS = {{"TOP", "RIGHT", "BOTTOM", "LEFT"}}; //String versions of side orientations
187+
188+
constexpr std::array<e_side, NUM_3D_SIDES> TOTAL_3D_SIDES = {{TOP, RIGHT, BOTTOM, LEFT, ABOVE, UNDER}}; //Set of all side orientations including different layers
189+
constexpr std::array<const char*, NUM_3D_SIDES> TOTAL_3D_SIDE_STRINGS = {{"TOP", "RIGHT", "BOTTOM", "LEFT", "ABOVE", "UNDER"}}; //String versions of side orientations including different layers
183190

184191
/* pin location distributions */
185192
enum class e_pin_location_distr {
@@ -822,10 +829,11 @@ struct t_physical_pin {
822829

823830
/**
824831
* @brief Describes The location of a physical tile
825-
* @param layer_num The die number of the physical tile. If the FPGA only has one die, or the physical tile is located
826-
* on the base die, layer_num is equal to zero. If it is one the die above base die, it is one, etc.
827832
* @param x The x location of the physical tile on the given die
828833
* @param y The y location of the physical tile on the given die
834+
* @param layer_num The die number of the physical tile. If the FPGA only has one die, or the physical tile is located
835+
* on the base die, layer_num is equal to zero. If the physical tile is location on the die immediately
836+
* above the base die, the layer_num is 1 and so on.
829837
*/
830838
struct t_physical_tile_loc {
831839
int x = OPEN;
@@ -1285,7 +1293,6 @@ class t_pb_graph_node {
12851293
int total_pb_pins; /* only valid for top-level */
12861294

12871295
void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */
1288-
t_cluster_placement_primitive* cluster_placement_primitive; /* pointer to indexing structure useful during packing stage */
12891296

12901297
int* input_pin_class_size; /* Stores the number of pins that belong to a particular input pin class */
12911298
int num_input_pin_class; /* number of input pin classes that this pb_graph_node has */
@@ -1975,10 +1982,12 @@ struct t_router {
19751982

19761983
/** A value representing the approximate horizontal position on the FPGA device where the router
19771984
* tile is located*/
1978-
double device_x_position = -1;
1985+
float device_x_position = -1;
19791986
/** A value representing the approximate vertical position on the FPGA device where the router
19801987
* tile is located*/
1981-
double device_y_position = -1;
1988+
float device_y_position = -1;
1989+
/** A value representing the exact layer in the FPGA device where the router tile is located.*/
1990+
int device_layer_position = -1;
19821991

19831992
/** A list of router ids that are connected to the current router*/
19841993
std::vector<int> connection_list;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -480,7 +480,7 @@ struct ArchReader {
480480
type.pin_height_offset.resize(type.num_pins, 0);
481481

482482
type.pinloc.resize({1, 1, 4}, std::vector<bool>(type.num_pins, false));
483-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
483+
for (e_side side : TOTAL_2D_SIDES) {
484484
for (int pin = 0; pin < type.num_pins; pin++) {
485485
type.pinloc[0][0][side][pin] = true;
486486
type.pin_width_offset[pin] = 0;

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -579,7 +579,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
579579
int num_sides = 4 * (type->width * type->height);
580580
int side_index = 0;
581581
int count = 0;
582-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
582+
for (e_side side : TOTAL_2D_SIDES) {
583583
for (int width = 0; width < type->width; ++width) {
584584
for (int height = 0; height < type->height; ++height) {
585585
for (int pin_offset = 0; pin_offset < (type->num_pins / num_sides) + 1; ++pin_offset) {
@@ -604,7 +604,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
604604
while (ipin < type->num_pins) {
605605
for (int width = 0; width < type->width; ++width) {
606606
for (int height = 0; height < type->height; ++height) {
607-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
607+
for (e_side side : TOTAL_2D_SIDES) {
608608
if (((width == 0 && side == LEFT)
609609
|| (height == type->height - 1 && side == TOP)
610610
|| (width == type->width - 1 && side == RIGHT)
@@ -645,7 +645,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
645645
while (ipin < input_pins.size()) {
646646
for (int width = 0; width < type->width; ++width) {
647647
for (int height = 0; height < type->height; ++height) {
648-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
648+
for (e_side side : TOTAL_2D_SIDES) {
649649
if (ipin < input_pins.size()) {
650650
//Pins still to allocate
651651

@@ -668,7 +668,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
668668
while (ipin < output_pins.size()) {
669669
for (int width = 0; width < type->width; ++width) {
670670
for (int height = 0; height < type->height; ++height) {
671-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
671+
for (e_side side : TOTAL_2D_SIDES) {
672672
if (((width == 0 && side == LEFT)
673673
|| (height == type->height - 1 && side == TOP)
674674
|| (width == type->width - 1 && side == RIGHT)
@@ -699,8 +699,8 @@ static void LoadPinLoc(pugi::xml_node Locations,
699699
for (int layer = 0; layer < num_of_avail_layer; ++layer) {
700700
for (int width = 0; width < type->width; ++width) {
701701
for (int height = 0; height < type->height; ++height) {
702-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
703-
for (const auto& token : pin_locs->assignments[sub_tile_index][width][height][layer][side]) {
702+
for (e_side side : TOTAL_2D_SIDES) {
703+
for (auto token : pin_locs->assignments[sub_tile_index][width][height][layer][side]) {
704704
auto pin_range = ProcessPinString<t_sub_tile*>(Locations,
705705
&sub_tile,
706706
token.c_str(),
@@ -3393,9 +3393,9 @@ static void ProcessPinLocations(pugi::xml_node Locations,
33933393
for (int l = 0; l < num_of_avail_layer; ++l) {
33943394
for (int w = 0; w < PhysicalTileType->width; ++w) {
33953395
for (int h = 0; h < PhysicalTileType->height; ++h) {
3396-
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
3397-
for (const auto& token : pin_locs->assignments[sub_tile_index][w][h][l][side]) {
3398-
InstPort inst_port(token);
3396+
for (e_side side : TOTAL_2D_SIDES) {
3397+
for (auto token : pin_locs->assignments[sub_tile_index][w][h][l][side]) {
3398+
InstPort inst_port(token.c_str());
33993399

34003400
//A pin specification should contain only the block name, and not any instance count information
34013401
if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) {
@@ -4766,9 +4766,9 @@ static int find_switch_by_name(const t_arch& arch, const std::string& switch_nam
47664766
}
47674767

47684768
static e_side string_to_side(const std::string& side_str) {
4769-
e_side side = NUM_SIDES;
4769+
e_side side = NUM_2D_SIDES;
47704770
if (side_str.empty()) {
4771-
side = NUM_SIDES;
4771+
side = NUM_2D_SIDES;
47724772
} else if (side_str == "left") {
47734773
side = LEFT;
47744774
} else if (side_str == "right") {

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