Skip to content

Commit 5261d67

Browse files
committed
dev: subtree config: remove trailing spaces and add interchange schema
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent a6e200e commit 5261d67

File tree

1 file changed

+32
-27
lines changed

1 file changed

+32
-27
lines changed

dev/subtree_config.xml

Lines changed: 32 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,47 @@
11
<subtrees>
2-
<subtree
3-
name="abc"
4-
internal_path="abc"
2+
<subtree
3+
name="abc"
4+
internal_path="abc"
55
external_url="https://github.com/berkeley-abc/abc.git"
66
default_external_ref="master"/>
7-
<subtree
7+
<subtree
88
name="libargparse"
99
internal_path="libs/EXTERNAL/libargparse"
1010
external_url="https://github.com/kmurray/libargparse.git"
1111
default_external_ref="master"/>
12-
<subtree
13-
name="libblifparse"
14-
internal_path="libs/EXTERNAL/libblifparse"
15-
external_url="https://github.com/verilog-to-routing/libblifparse.git"
12+
<subtree
13+
name="libblifparse"
14+
internal_path="libs/EXTERNAL/libblifparse"
15+
external_url="https://github.com/verilog-to-routing/libblifparse.git"
1616
default_external_ref="master"/>
17-
<subtree
18-
name="libsdcparse"
19-
internal_path="libs/EXTERNAL/libsdcparse"
20-
external_url="https://github.com/verilog-to-routing/libsdcparse.git"
17+
<subtree
18+
name="libsdcparse"
19+
internal_path="libs/EXTERNAL/libsdcparse"
20+
external_url="https://github.com/verilog-to-routing/libsdcparse.git"
2121
default_external_ref="master"/>
22-
<subtree
23-
name="libtatum"
24-
internal_path="libs/EXTERNAL/libtatum"
25-
external_url="https://github.com/verilog-to-routing/tatum.git"
22+
<subtree
23+
name="libtatum"
24+
internal_path="libs/EXTERNAL/libtatum"
25+
external_url="https://github.com/verilog-to-routing/tatum.git"
2626
default_external_ref="master"/>
27-
<subtree
28-
name="libezgl"
29-
internal_path="libs/EXTERNAL/libezgl"
30-
external_url="https://github.com/mariobadr/ezgl.git"
27+
<subtree
28+
name="libezgl"
29+
internal_path="libs/EXTERNAL/libezgl"
30+
external_url="https://github.com/mariobadr/ezgl.git"
3131
default_external_ref="master"/>
32-
<subtree
33-
name="capnproto"
34-
internal_path="libs/EXTERNAL/capnproto"
35-
external_url="https://github.com/capnproto/capnproto.git"
32+
<subtree
33+
name="capnproto"
34+
internal_path="libs/EXTERNAL/capnproto"
35+
external_url="https://github.com/capnproto/capnproto.git"
3636
default_external_ref="v0.7.0"/>
37-
<subtree
38-
name="libyosys"
39-
internal_path="libs/EXTERNAL/libyosys"
37+
<subtree
38+
name="libyosys"
39+
internal_path="libs/EXTERNAL/libyosys"
4040
external_url="https://github.com/YosysHQ/yosys.git"
4141
default_external_ref="master"/>
42+
<subtree
43+
name="libinterchange"
44+
internal_path="libs/EXTERNAL/libinterchange"
45+
external_url="https://github.com/chipsalliance/fpga-interchange-schema.git"
46+
default_external_ref="main"/>
4247
</subtrees>

0 commit comments

Comments
 (0)