Skip to content

Commit 4e0fcb9

Browse files
acomodiacomodi
committed
equivalent: clb_directs should affect phy tiles and not log blocks
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent f1fe0e6 commit 4e0fcb9

File tree

1 file changed

+48
-39
lines changed

1 file changed

+48
-39
lines changed

‎vpr/src/route/rr_graph.cpp

Lines changed: 48 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,10 @@ struct t_mux_size_distribution {
5151
};
5252

5353
struct t_clb_to_clb_directs {
54-
t_logical_block_type_ptr from_clb_type;
54+
t_physical_tile_type_ptr from_clb_type;
5555
int from_clb_pin_start_index;
5656
int from_clb_pin_end_index;
57-
t_logical_block_type_ptr to_clb_type;
57+
t_physical_tile_type_ptr to_clb_type;
5858
int to_clb_pin_start_index;
5959
int to_clb_pin_end_index;
6060
int switch_index; //The switch type used by this direct connection
@@ -2653,94 +2653,103 @@ static void build_unidir_rr_opins(const int i, const int j, const e_side side, c
26532653
* TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one
26542654
*/
26552655
static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) {
2656-
int i, j;
2657-
unsigned int itype;
2656+
int i;
26582657
t_clb_to_clb_directs* clb_to_clb_directs;
2659-
char *pb_type_name, *port_name;
2658+
char *tile_name, *port_name;
26602659
int start_pin_index, end_pin_index;
2661-
t_pb_type* pb_type;
2660+
t_physical_tile_type_ptr physical_tile = nullptr;
2661+
t_physical_tile_port tile_port;
26622662

26632663
auto& device_ctx = g_vpr_ctx.device();
26642664

26652665
clb_to_clb_directs = (t_clb_to_clb_directs*)vtr::calloc(num_directs, sizeof(t_clb_to_clb_directs));
26662666

2667-
pb_type_name = nullptr;
2667+
tile_name = nullptr;
26682668
port_name = nullptr;
26692669

26702670
for (i = 0; i < num_directs; i++) {
2671-
pb_type_name = (char*)vtr::malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char));
2671+
tile_name = (char*)vtr::malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char));
26722672
port_name = (char*)vtr::malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char));
26732673

26742674
// Load from pins
26752675
// Parse out the pb_type name, port name, and pin range
2676-
parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name);
2676+
parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, tile_name, port_name);
26772677

26782678
// Figure out which type, port, and pin is used
2679-
for (itype = 0; itype < device_ctx.logical_block_types.size(); ++itype) {
2680-
if (strcmp(device_ctx.logical_block_types[itype].name, pb_type_name) == 0) {
2679+
for (auto& type : device_ctx.physical_tile_types) {
2680+
if (strcmp(type.name, tile_name) == 0) {
2681+
physical_tile = &type;
26812682
break;
26822683
}
26832684
}
26842685

2685-
if (itype >= device_ctx.logical_block_types.size()) {
2686-
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line, "Unable to find block %s.\n", pb_type_name);
2686+
if (physical_tile == nullptr) {
2687+
VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name);
26872688
}
26882689

2689-
clb_to_clb_directs[i].from_clb_type = &device_ctx.logical_block_types[itype];
2690-
pb_type = clb_to_clb_directs[i].from_clb_type->pb_type;
2690+
clb_to_clb_directs[i].from_clb_type = physical_tile;
26912691

2692-
for (j = 0; j < pb_type->num_ports; j++) {
2693-
if (strcmp(pb_type->ports[j].name, port_name) == 0) {
2692+
bool port_found = false;
2693+
for (auto port : physical_tile->ports) {
2694+
if (0 == strcmp(port.name, port_name)) {
2695+
tile_port = port;
2696+
port_found = true;
26942697
break;
26952698
}
26962699
}
2697-
if (j >= pb_type->num_ports) {
2698-
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line, "Unable to find port %s (on block %s).\n", port_name, pb_type_name);
2700+
2701+
if (!port_found) {
2702+
VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, tile_name);
26992703
}
27002704

27012705
if (start_pin_index == OPEN) {
27022706
VTR_ASSERT(start_pin_index == end_pin_index);
27032707
start_pin_index = 0;
2704-
end_pin_index = pb_type->ports[j].num_pins - 1;
2708+
end_pin_index = tile_port.num_pins - 1;
27052709
}
2706-
get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].from_clb_pin_start_index);
2707-
get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].from_clb_pin_end_index);
2710+
2711+
clb_to_clb_directs[i].from_clb_pin_start_index = tile_port.absolute_first_pin_index + start_pin_index;
2712+
clb_to_clb_directs[i].from_clb_pin_end_index = tile_port.absolute_first_pin_index + end_pin_index;
27082713

27092714
// Load to pins
27102715
// Parse out the pb_type name, port name, and pin range
2711-
parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name);
2716+
parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, tile_name, port_name);
27122717

27132718
// Figure out which type, port, and pin is used
2714-
for (itype = 0; itype < device_ctx.logical_block_types.size(); ++itype) {
2715-
if (strcmp(device_ctx.logical_block_types[itype].name, pb_type_name) == 0) {
2719+
for (auto& type : device_ctx.physical_tile_types) {
2720+
if (strcmp(type.name, tile_name) == 0) {
2721+
physical_tile = &type;
27162722
break;
27172723
}
27182724
}
27192725

2720-
if (itype >= device_ctx.logical_block_types.size()) {
2721-
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line, "Unable to find block %s.\n", pb_type_name);
2726+
if (physical_tile == nullptr) {
2727+
VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name);
27222728
}
27232729

2724-
clb_to_clb_directs[i].to_clb_type = &device_ctx.logical_block_types[itype];
2725-
pb_type = clb_to_clb_directs[i].to_clb_type->pb_type;
2730+
clb_to_clb_directs[i].from_clb_type = physical_tile;
27262731

2727-
for (j = 0; j < pb_type->num_ports; j++) {
2728-
if (strcmp(pb_type->ports[j].name, port_name) == 0) {
2732+
port_found = false;
2733+
for (auto port : physical_tile->ports) {
2734+
if (0 == strcmp(port.name, port_name)) {
2735+
tile_port = port;
2736+
port_found = true;
27292737
break;
27302738
}
27312739
}
2732-
if (j >= pb_type->num_ports) {
2733-
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line, "Unable to find port %s (on block %s).\n", port_name, pb_type_name);
2740+
2741+
if (!port_found) {
2742+
VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, tile_name);
27342743
}
27352744

27362745
if (start_pin_index == OPEN) {
27372746
VTR_ASSERT(start_pin_index == end_pin_index);
27382747
start_pin_index = 0;
2739-
end_pin_index = pb_type->ports[j].num_pins - 1;
2748+
end_pin_index = tile_port.num_pins - 1;
27402749
}
27412750

2742-
get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].to_clb_pin_start_index);
2743-
get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].to_clb_pin_end_index);
2751+
clb_to_clb_directs[i].to_clb_pin_start_index = tile_port.absolute_first_pin_index + start_pin_index;
2752+
clb_to_clb_directs[i].to_clb_pin_end_index = tile_port.absolute_first_pin_index + end_pin_index;
27442753

27452754
if (abs(clb_to_clb_directs[i].from_clb_pin_start_index - clb_to_clb_directs[i].from_clb_pin_end_index) != abs(clb_to_clb_directs[i].to_clb_pin_start_index - clb_to_clb_directs[i].to_clb_pin_end_index)) {
27462755
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line,
@@ -2755,7 +2764,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
27552764
//Use the delayless switch by default
27562765
clb_to_clb_directs[i].switch_index = delayless_switch;
27572766
}
2758-
free(pb_type_name);
2767+
free(tile_name);
27592768
free(port_name);
27602769

27612770
//We must be careful to clean-up anything that we may have incidentally allocated.
@@ -2803,7 +2812,7 @@ static int get_opin_direct_connecions(int x,
28032812
/* Iterate through all direct connections */
28042813
for (int i = 0; i < num_directs; i++) {
28052814
/* Find matching direct clb-to-clb connections with the same type as current grid location */
2806-
if (clb_to_clb_directs[i].from_clb_type == logical_block_type(curr_type)) { //We are at a valid starting point
2815+
if (clb_to_clb_directs[i].from_clb_type == curr_type) { //We are at a valid starting point
28072816

28082817
if (directs[i].from_side != NUM_SIDES && directs[i].from_side != side) continue;
28092818

@@ -2814,7 +2823,7 @@ static int get_opin_direct_connecions(int x,
28142823
&& y + directs[i].y_offset > 0) {
28152824
//Only add connections if the target clb type matches the type in the direct specification
28162825
t_physical_tile_type_ptr target_type = device_ctx.grid[x + directs[i].x_offset][y + directs[i].y_offset].type;
2817-
if (clb_to_clb_directs[i].to_clb_type == logical_block_type(target_type)
2826+
if (clb_to_clb_directs[i].to_clb_type == target_type
28182827
&& z + directs[i].z_offset < int(target_type->capacity)
28192828
&& z + directs[i].z_offset >= 0) {
28202829
/* Compute index of opin with regards to given pins */

0 commit comments

Comments
 (0)