File tree 5 files changed +16
-16
lines changed
vtr_flow/tasks/regression_tests
vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config
strong_clock_aliases/config
strong_clock_aliases_set_delay/config
strong_clock_modeling/config
strong_diff_mux_for_inc_dec_wires/config 5 files changed +16
-16
lines changed Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- k6_N10_40nm.xml stereovision0.v common 140.15 vpr 272.04 MiB -1 -1 12.85 119508 5 37.98 -1 -1 65828 -1 -1 1307 169 -1 -1 success v8.0.0-10642-gf11aaea3f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-07-18T10:51:58 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/ vtr-verilog-to-routing/vtr_flow/tasks 278564 169 197 21166 21363 1 7566 1673 39 39 1521 clb auto 140.8 MiB 3.95 53142 974519 347458 607168 19893 272.0 MiB 10.23 0.10 3.63366 -15348.4 -3.63366 3.63366 9.71 0.0315035 0.026913 3.45179 2.89228 44 69063 46 7.37824e +07 7.04408e +07 4.68145e +06 3077.88 43.27 19.1637 16.0718 125110 968779 -1 63965 24 33902 65662 2813140 489196 3.57565 3.57565 -16119.5 -3.57565 0 0 6.05227e +06 3979.14 1.97 2.96 0.84 -1 -1 1.97 2.09287 1.80452
3- k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 138.68 vpr 271.91 MiB -1 -1 12.57 119440 5 36.46 -1 -1 65388 -1 -1 1307 169 -1 -1 success v8.0.0-10642-gf11aaea3f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-07-18T10:51:58 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/ vtr-verilog-to-routing/vtr_flow/tasks 278432 169 197 21166 21363 1 7566 1673 39 39 1521 clb auto 140.7 MiB 3.96 53142 974519 347458 607168 19893 271.9 MiB 11.12 0.11 3.63366 -15348.4 -3.63366 3.63366 9.48 0.037164 0.0323029 4.04546 3.42407 44 69063 46 7.37824e+07 7.04408e +07 4.68145e +06 3077.88 43 .94 19.9593 16.7643 125110 968779 -1 63965 24 33902 65662 2813140 489196 3.57565 3.57565 -16119.5 -3.57565 0 0 6.05227e +06 3979.14 2.02 2.80 0.83 -1 -1 2.02 1.87812 1.62699
2+ k6_N10_40nm.xml stereovision0.v common 122.65 vpr 276.58 MiB -1 -1 16.00 124916 5 53.73 -1 -1 69176 -1 -1 1305 169 -1 -1 success 28100b1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:45:19 gh-actions-runner-vtr-auto-spawned39 /root/ vtr-verilog-to-routing/vtr-verilog-to-routing 283220 169 197 21117 21314 1 7688 1671 39 39 1521 clb auto 143.1 MiB 2.85 53732 982959 351248 609845 21866 276.6 MiB 9.99 0.10 3.76204 -15507.8 -3.76204 3.76204 9.44 0.0159737 0.0133362 1.80765 1.48264 42 70545 48 2.4642e +07 2.349e +07 4.65856e +06 3062.82 15.47 6.76385 5.69 122070 947469 -1 65863 22 34742 65762 3361891 541264 4.0937 4.0937 -16235.4 -4.0937 0 0 5.79504e +06 3810.02 1.92 1.71 0.57 -1 -1 1.92 1.12349 0.992148
3+ k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 134.93 vpr 274.07 MiB -1 -1 16.21 125172 5 55.27 -1 -1 68860 -1 -1 1305 169 -1 -1 success 28100b1 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:45:19 gh-actions-runner-vtr-auto-spawned39 /root/ vtr-verilog-to-routing/vtr-verilog-to-routing 280648 169 197 21117 21314 1 7523 1671 39 39 1521 clb auto 143.0 MiB 2.85 51811 1022607 376856 616274 29477 274.1 MiB 10.32 0.10 3.69006 -14773.1 -3.69006 3.69006 9.39 0.0156983 0.0130538 1.86259 1.52838 38 69466 48 7.37824e+07 7.0333e +07 4.16760e +06 2740.04 25 .94 8.42194 7.05848 119030 845795 -1 62788 23 35878 68950 2803037 507578 3.5696 3.5696 -16170.3 -3.5696 0 0 5.22668e +06 3436.35 1.75 1.68 0.49 -1 -1 1.75 1.12315 0.986398
Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 4.34 vpr 203.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 884dcc8 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-25T20:48:27 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208364 1 4 28 32 2 10 9 4 4 16 clb auto 51.8 MiB 0.15 20 27 15 8 4 194.0 MiB 0.03 0.00 2.44626 0 0 2.44626 0.52 0.000590751 0.000540821 0.00316208 0.00264441 8 12 5 72000 72000 5593.62 349.601 0.90 0.0650926 0.0576217 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0118781 0.0104259
3- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 4.30 vpr 203.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 884dcc8 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-25T20:48:27 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208860 1 4 28 32 2 10 9 4 4 16 clb auto 52.0 MiB 0.15 20 27 15 8 4 194.0 MiB 0.03 0.00 2.44626 0 0 2.44626 0.53 0.000590039 0.000540401 0.00316168 0.00264575 8 12 5 72000 72000 5593.62 349.601 0.91 0.0661082 0.058795 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.011084 0.00968987
4- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 4.36 vpr 202.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 884dcc8 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-25T20:48:27 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 207564 1 4 28 32 2 10 9 4 4 16 clb auto 51.6 MiB 0.15 20 27 15 8 4 193.4 MiB 0.03 0.00 2.44626 0 0 2.44626 0.52 0.000584676 0.000538033 0.00319424 0.00261523 8 12 5 72000 72000 5593.62 349.601 0.91 0.0673054 0.0593848 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.18 -1 -1 0.01 0.0112706 0.00986656
2+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 4.07 vpr 203.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 28100b1 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:49:29 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208244 1 4 28 32 2 10 9 4 4 16 clb auto 52.2 MiB 0.14 20 27 15 8 4 193.9 MiB 0.03 0.00 2.44626 0 0 2.44626 0.50 0.000571891 0.000524572 0.00307425 0.00256774 8 12 5 72000 72000 5593.62 349.601 0.85 0.0613454 0.0545823 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.010792 0.00942798
3+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 4.11 vpr 203.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 28100b1 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:49:29 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208224 1 4 28 32 2 10 9 4 4 16 clb auto 51.7 MiB 0.14 20 27 15 8 4 193.4 MiB 0.03 0.00 2.44626 0 0 2.44626 0.50 0.00058752 0.000534007 0.00311595 0.0026124 8 12 5 72000 72000 5593.62 349.601 0.83 0.0566783 0.0504183 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0110182 0.00964784
4+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 5.95 vpr 203.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success 28100b1 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:49:29 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 208644 1 4 28 32 2 10 9 4 4 16 clb auto 52.1 MiB 0.14 20 27 15 8 4 193.9 MiB 0.03 0.00 2.44626 0 0 2.44626 0.48 0.000574077 0.000526413 0.00309971 0.00259288 8 12 5 72000 72000 5593.62 349.601 0.85 0.061428 0.0545572 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.01 0.04 0.17 -1 -1 0.01 0.0109867 0.00962922
Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 3.91 vpr 201.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 884dcc8 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-25T20:48:27 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 205860 2 2 22 24 2 4 6 4 4 16 clb auto 51.6 MiB 0.11 4 15 2 10 3 193.0 MiB 0.02 0.00 1.297 0 0 1.297 0.53 0.000520067 0.000476752 0.00285601 0.00232812 4 6 2 72000 36000 2827.54 176.721 0.63 0.0112241 0.0092358 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.03 0.17 -1 -1 0.01 0.00632552 0.00538297
2+ timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 3.64 vpr 201.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 28100b1 -dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-26T22:49:29 gh-actions-runner-vtr-auto-spawned147 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 206076 2 2 22 24 2 4 6 4 4 16 clb auto 51.9 MiB 0.10 4 15 2 10 3 193.2 MiB 0.02 0.00 1.297 0 0 1.297 0.50 0.00047801 0.000438708 0.00256566 0.00209288 4 6 2 72000 36000 2827.54 176.721 0.59 0.0102637 0.00844197 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00594057 0.00506721
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