Merge branch 'master' into m1

Author: vaughnbetz

.github/scripts/hostsetup.sh

@@ -30,7 +30,6 @@ apt install -y \
   build-essential \
   capnproto \
   clang \
-  cmake \
   ctags \
   curl \
   doxygen \
@@ -65,12 +64,23 @@ apt install -y \
   valgrind \
   zip \
   qt5-default \
+  uuid-dev \
+  default-jdk \
   g++-9 \
   gcc-9 \
   wget
   # Don't include libtbb-dev since it may increase memory usage
   #libtbb-dev \
 
+# installing the latest version of cmake
+apt install -y apt-transport-https ca-certificates gnupg
+wget -qO - https://apt.kitware.com/keys/kitware-archive-latest.asc |apt-key add -
+
+apt-add-repository 'deb https://apt.kitware.com/ubuntu/ bionic main'
+apt update
+apt install -y cmake
+
+
 export PATH="$PATH:/home/kbuilder/.local/bin"
 
 export CC=gcc-9

.github/scripts/install_dependencies.sh

@@ -39,6 +39,8 @@ sudo apt install -y \
   valgrind \
   zip \
   qt5-default \
+  uuid-dev \
+  default-jdk \
   clang-format-7 \
   g++-7 \
   gcc-7 \

.github/workflows/test.yml

@@ -32,8 +32,8 @@ jobs:
           - {test: "vtr_reg_nightly_test4", cores: "16", options: "",          cmake: ""                                             }
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3"                         }
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON"}
-          - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON"                              }
-          - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON"                          }
+          - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON"    }
+          - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON"}
           - {test: "odin_tech_strong",      cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON"                          }
           - {test: "odin_reg_strong",       cores: "16", options: "",          cmake: ""                                             }
 

.gitignore

@@ -12,6 +12,7 @@ bin/
 CMakeCache.txt
 CMakeFiles
 build
+Yosys
 
 #
 #VTR Flow/Tasks
@@ -105,6 +106,11 @@ ODIN_II/usefull_tools/**/track_completed
 #
 Yosys
 
+#
+#ArchFPGA exec dir
+#
+ArchFPGA
+
 #
 #Python
 #

CMakeLists.txt

@@ -55,6 +55,7 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 # Allow the user to enable building Yosys
 option(WITH_YOSYS "Enable building Yosys" OFF)
 option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
+option(YOSYS_SV_UHDM_PLUGIN "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
 
 set(VTR_VERSION_MAJOR 8)
 set(VTR_VERSION_MINOR 1)
@@ -398,6 +399,14 @@ elseif(${WITH_ODIN})
     endif()
 endif()
 
+# handle cmake params to compile Yosys SystemVerilog/UHDM plugins
+if(${YOSYS_SV_UHDM_PLUGIN})
+    # avoid compiling plugins in case the Yosys frontend is not active
+    if(NOT ${WITH_YOSYS} AND NOT ${ODIN_USE_YOSYS})
+        message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Yosys frontend. Please set either WITH_YOSYS or ODIN_USE_YOSYS on.")
+    endif()
+endif()
+
 #Add extra compilation flags to suppress warnings from some libraries/tools
 # Note that target_compile_options() *appends* to the current compilation options of
 # the specified target

ODIN_II/CMakeLists.txt

@@ -7,8 +7,8 @@ if(ODIN_DEBUG)
     message("*** Compiling with Odin debug flags")
 
     set(ODIN_EXTRA_FLAGS
-        "-g"
-        "-ggdb"
+        "-g3"
+        "-ggdb3"
         "-O0"
         ${ODIN_EXTRA_FLAGS}
     )
@@ -136,6 +136,9 @@ endif()
 if(${ODIN_USE_YOSYS})
     add_definitions("-DODIN_USE_YOSYS=ON")
     add_definitions("-D_YOSYS_")
+    if(${YOSYS_SV_UHDM_PLUGIN})
+        add_definitions("-DYOSYS_SV_UHDM_PLUGIN=ON")
+    endif()
 endif()
 
 add_definitions(-DUSING_BISON -DYYERROR_VERBOSE)

ODIN_II/SRC/BLIFElaborate.cpp

@@ -50,6 +50,7 @@
 #include "hard_blocks.h"
 #include "memories.h"
 #include "BlockMemories.hpp"
+#include "BitwiseOps.hpp"
 #include "LogicalOps.hpp"
 #include "memories.h"
 #include "adders.h"
@@ -72,6 +73,7 @@ void depth_first_traverse_blif_elaborate(nnode_t* node, uintptr_t traverse_mark_
 
 void blif_elaborate_node(nnode_t* node, short traverse_mark_number, netlist_t* netlist);
 
+static void resolve_bitwise_nodes(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
 static void resolve_logical_nodes(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
 static void resolve_shift_nodes(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
 static void resolve_case_equal_nodes(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
@@ -200,6 +202,19 @@ void depth_first_traverse_blif_elaborate(nnode_t* node, uintptr_t traverse_mark_
  *--------------------------------------------------------------------*/
 void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlist) {
     switch (node->type) {
+        case BITWISE_NOT:  //fallthrough
+        case BITWISE_AND:  //fallthrough
+        case BITWISE_OR:   //fallthrough
+        case BITWISE_NAND: //fallthrough
+        case BITWISE_NOR:  //fallthrough
+        case BITWISE_XNOR: //fallthrough
+        case BITWISE_XOR: {
+            /** 
+             * make sure they have only two inputs and a single output pin for partial mapping phase 
+             */
+            resolve_bitwise_nodes(node, traverse_number, netlist);
+            break;
+        }
         case GTE:           //fallthrough
         case LTE:           //fallthrough
         case GT:            //fallthrough
@@ -296,20 +311,13 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
             resolve_memory_nodes(node, traverse_number, netlist);
             break;
         }
-        case GND_NODE:     //fallthrough
-        case VCC_NODE:     //fallthrough
-        case PAD_NODE:     //fallthrough
-        case INPUT_NODE:   //fallthrough
-        case OUTPUT_NODE:  //fallthrough
-        case HARD_IP:      //fallthrough
-        case BUF_NODE:     //fallthrough
-        case BITWISE_NOT:  //fallthrough
-        case BITWISE_AND:  //fallthrough
-        case BITWISE_OR:   //fallthrough
-        case BITWISE_NAND: //fallthrough
-        case BITWISE_NOR:  //fallthrough
-        case BITWISE_XNOR: //fallthrough
-        case BITWISE_XOR: {
+        case GND_NODE:    //fallthrough
+        case VCC_NODE:    //fallthrough
+        case PAD_NODE:    //fallthrough
+        case INPUT_NODE:  //fallthrough
+        case OUTPUT_NODE: //fallthrough
+        case HARD_IP:     //fallthrough
+        case BUF_NODE: {
             /* some are already resolved for this phase */
             break;
         }
@@ -323,6 +331,45 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
     }
 }
 
+/**
+ * (function: resolve_bitwise_nodes)
+ * 
+ * @brief resolving the bitwise nodes by decoding them into 2-1 nodes
+ * 
+ * @param node pointing to a bitwise node 
+ * @param traverse_mark_number unique traversal mark for blif elaboration pass
+ * @param netlist pointer to the current netlist file
+ */
+static void resolve_bitwise_nodes(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist) {
+    oassert(node->traverse_visited == traverse_mark_number);
+
+    switch (node->type) {
+        case BITWISE_XNOR: //fallthrough
+        case BITWISE_XOR: {
+            /**
+             * decode bitwise nodes into nodes with 2 input and 1 output
+             * only for reduction operation
+             */
+            if (node->num_output_pins == 1)
+                decode_bitwise_nodes(node, traverse_mark_number, netlist);
+            break;
+        }
+        case BITWISE_NOT:  //fallthrough
+        case BITWISE_AND:  //fallthrough
+        case BITWISE_OR:   //fallthrough
+        case BITWISE_NAND: //fallthrough
+        case BITWISE_NOR: {
+            /* to be handled in partial map */
+            break;
+        }
+        default: {
+            error_message(BLIF_ELABORATION, node->loc,
+                          "The node(%s) type is not among Odin's bitwise types [BITWISE_NOT, BITWISE_AND, BITWISE_OR, BITWISE_NAND, BITWISE_NOR, BITWISE_XNOR, BITWISE_XOR]\n", node->name);
+            break;
+        }
+    }
+}
+
 /**
  * (function: resolve_logical_nodes)
  * 

ODIN_II/SRC/BLIFReader.cpp

@@ -348,18 +348,18 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
         /* check for coarse-grain configuration */
         if (configuration.coarsen) {
             if (yosys_subckt_strmap.find(subcircuit_name) != yosys_subckt_strmap.end())
-                new_node->type = yosys_subckt_strmap[subcircuit_name];
+                new_node->type = yosys_subckt_strmap.at(subcircuit_name);
 
             if (new_node->type == NO_OP && yosys_subckt_strmap.find(subcircuit_stripped_name) != yosys_subckt_strmap.end())
-                new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
+                new_node->type = yosys_subckt_strmap.at(subcircuit_stripped_name);
 
             if (new_node->type == NO_OP) {
                 /* in case of weird names, need to add memories manually */
                 int sc_spot = -1;
                 char* yosys_subckt_str = NULL;
                 if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
                     /* specify node type */
-                    new_node->type = yosys_subckt_strmap[yosys_subckt_str];
+                    new_node->type = yosys_subckt_strmap.at(yosys_subckt_str);
                 } else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
                     /* specify node type */
                     new_node->type = HARD_IP;
@@ -387,11 +387,14 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
                                            : operation_list_END;
             }
         } else {
-            new_node->type = odin_subckt_strmap[subcircuit_name];
+            if (odin_subckt_strmap.find(subcircuit_name) != odin_subckt_strmap.end())
+                new_node->type = odin_subckt_strmap.at(subcircuit_name);
 
             /* check for subcircuit prefix prefix */
-            if (subcircuit_stripped_name && new_node->type == NO_OP)
-                new_node->type = odin_subckt_strmap[subcircuit_stripped_name];
+            if (subcircuit_stripped_name
+                && new_node->type == NO_OP
+                && odin_subckt_strmap.find(subcircuit_stripped_name) != odin_subckt_strmap.end())
+                new_node->type = odin_subckt_strmap.at(subcircuit_stripped_name);
 
             if (new_node->type == NO_OP)
                 new_node->type = MEMORY;
@@ -2050,6 +2053,8 @@ hard_block_model* BLIF::Reader::create_hard_block_model(const char* name, operat
         case (BITWISE_OR):     //fallthrough
         case (BITWISE_NOT):    //fallthrough
         case (BITWISE_AND):    //fallthrough
+        case (BITWISE_XOR):    //fallthrough
+        case (BITWISE_XNOR):   //fallthrough
         case (LOGICAL_OR):     //fallthrough
         case (LOGICAL_XOR):    //fallthrough
         case (LOGICAL_AND):    //fallthrough
@@ -2176,7 +2181,7 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
     char* buffer = NULL;
     attr_t* attributes = new_node->attributes;
     operation_list op = (yosys_subckt_strmap.find(subckt_name) != yosys_subckt_strmap.end())
-                            ? yosys_subckt_strmap[subckt_name]
+                            ? yosys_subckt_strmap.at(subckt_name)
                             : NO_OP;
 
     if (need_params(op)) {