[Odin]: cleaning up the old soft mult node after splitting

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

ODIN_II/.gitattributes

@@ -61,6 +61,7 @@ void split_soft_multiplier(nnode_t* node, netlist_t* netlist);
 static mult_port_stat_e is_constant_multipication(nnode_t* node, netlist_t* netlist);
 static signal_list_t* implement_constant_multipication(nnode_t* node, mult_port_stat_e port_status, short mark, netlist_t* netlist);
 static nnode_t* perform_const_mult_optimization(mult_port_stat_e mult_port_stat, nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
+static void cleanup_mult_old_node(nnode_t* nodeo, netlist_t* netlist);
 
 // data structure representing a row of bits an adder tree
 struct AdderTreeRow {
@@ -1527,15 +1528,9 @@ void split_soft_multiplier(nnode_t* node, netlist_t* netlist) {
         }
     }
 
-    // Probably more to do here in freeing the old node!
-    vtr::free(node->name);
-    vtr::free(node->input_port_sizes);
-    vtr::free(node->output_port_sizes);
+    // CLEAN UP
+    cleanup_mult_old_node(node, netlist);
 
-    // Free arrays NOT the pins since relocated!
-    vtr::free(node->input_pins);
-    vtr::free(node->output_pins);
-    vtr::free(node);
 }
 
 /**
@@ -1757,6 +1752,58 @@ void clean_multipliers() {
     return;
 }
 
+/**
+ * -------------------------------------------------------------------------
+ * (function: cleanup_mult_old_node)
+ *
+ * @brief <clean up nodeo, a high level MULT node> 
+ * In split_soft_multplier function, nodeo is splitted to small multipliers, 
+ * while because of the complexity of input pin connections they have not been 
+ * remapped to new nodes, they just copied and added to new nodes. This function 
+ * will detach input pins from the nodeo. Moreover, it will connect the net of 
+ * unconnected output signals to the GND node, detach the pin from nodeo and 
+ * free the output pins to avoid memory leak.
+ * 
+ * @param nodeo representing the old adder node
+ * @param netlist representing the current netlist
+ *-----------------------------------------------------------------------*/
+static void cleanup_mult_old_node(nnode_t* nodeo, netlist_t* netlist) {
+    int i;
+    /* Disconnecting input pins from the old node side */
+    for (i = 0; i < nodeo->num_input_pins; i++) {
+        nodeo->input_pins[i] = NULL;
+    }
+
+    /* connecting the extra output pins to the gnd node */
+    for (i = 0; i < nodeo->num_output_pins; i++) {
+        npin_t* output_pin = nodeo->output_pins[i];
+
+        if (output_pin && output_pin->node) {
+            /* for now we just pass the signals directly through */
+            npin_t* zero_pin = get_zero_pin(netlist);
+            int idx_2_buffer = zero_pin->pin_net_idx;
+
+            // Dont eliminate the buffer if there are multiple drivers or the AST included it
+            if (output_pin->net->num_driver_pins <= 1) {
+                /* join all fanouts of the output net with the input pins net */
+                join_nets(zero_pin->net, output_pin->net);
+
+                /* erase the pointer to this buffer */
+                zero_pin->net->fanout_pins[idx_2_buffer] = NULL;
+            }
+
+            free_npin(zero_pin);
+            free_npin(output_pin);
+
+            /* Disconnecting output pins from the old node side */
+            nodeo->output_pins[i] = NULL;
+        }
+    }
+
+    // CLEAN UP
+    free_nnode(nodeo);
+}
+
 void free_multipliers() {
     if (hard_multipliers && hard_multipliers->instances) {
         t_multiplier* tmp = (t_multiplier*)hard_multipliers->instances;

ODIN_II/SRC/multipliers.cpp

@@ -4,6 +4,7 @@
 
 //`define SIMULATION_MEMORY
 //`define SIMULATION_addfp
+
 `define VECTOR_DEPTH 64 //Q,K,V vector size
 `define DATA_WIDTH 16
 `define VECTOR_BITS 1024 // 16 bit each (16x64)

vtr_flow/benchmarks/verilog/koios/attention_layer.v

@@ -18,6 +18,7 @@
 // Abridged for VTR by: Daniel Rauch
 //////////////////////////////////////////////////////////////////////////////
 
+
 module dpram ( 
 
     clk, 

vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v

@@ -15,6 +15,7 @@
 //4. Double-buffering after each layer. 
 ///////////////////////////////////////////////////////////////////////////////
 
+
 module DLA (
 	input clk,
 	input i_reset,

vtr_flow/benchmarks/verilog/koios/dla_like.medium.v

@@ -15,6 +15,7 @@
 //4. Double-buffering after each layer. 
 ///////////////////////////////////////////////////////////////////////////////
 
+
 module DLA (
 	input clk,
 	input i_reset,

vtr_flow/benchmarks/verilog/koios/dla_like.small.v

@@ -56,6 +56,7 @@
 //section by section. The number of rows will be programmed
 //in the "iterations" register in the design.
 
+
 `define BFLOAT16 
 
 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10

vtr_flow/benchmarks/verilog/koios/eltwise_layer.v

@@ -19,6 +19,7 @@
 // with a simpler DSP (just a fixed point multiplier) like in the
 // flagship arch timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
 /////////////////////////////////////////////////////////////////////////
+
 `define BFLOAT16 
 
 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10

vtr_flow/benchmarks/verilog/koios/gemm_layer.v

@@ -14,6 +14,7 @@
 //////////////////////////////////////////////////////////////////////////////
 
 //softmax_p8_smem_rfloat16_alut_v512_b2_-0.1_0.1.v
+
 `ifndef DEFINES_DONE
 `define DEFINES_DONE
 `define EXPONENT 5

vtr_flow/benchmarks/verilog/koios/softmax.v

@@ -16,6 +16,7 @@
 //////////////////////////////////////////////////////////////////////////////
 
 `timescale 1 ns / 1 ps 
+
 module td_fused_top_Block_entry_proc_proc392 (
         ap_clk,
         ap_rst,