heterogeneous: address review comments

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

vpr/src/base/read_place.cpp

@@ -250,7 +250,7 @@ void read_user_pad_loc(const char* pad_loc_file) {
 
         auto physical_tile = device_ctx.grid[i][j].type;
         auto logical_block = cluster_ctx.clb_nlist.block_type(bnum);
-        if (!is_tile_compatible(physical_tile, logical_block, place_ctx.block_locs[bnum].loc)) {
+        if (!is_tile_compatible(physical_tile, logical_block, place_ctx.block_locs[bnum].loc.sub_tile)) {
             VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0,
                       "Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j);
         }

vpr/src/place/compressed_grid.cpp

@@ -23,8 +23,22 @@ std::vector<t_compressed_block_grid> create_compressed_block_grids() {
     }
 
     std::vector<t_compressed_block_grid> compressed_type_grids(device_ctx.logical_block_types.size());
-    for (const auto& type : device_ctx.logical_block_types) {
-        compressed_type_grids[type.index] = create_compressed_block_grid(block_locations[type.index]);
+    for (const auto& logical_block : device_ctx.logical_block_types) {
+        auto compressed_block_grid = create_compressed_block_grid(block_locations[logical_block.index]);
+
+        for (const auto& physical_tile : logical_block.equivalent_tiles) {
+            std::vector<int> compatible_sub_tiles;
+
+            for (int capacity = 0; capacity < physical_tile->capacity; capacity++) {
+                if (is_tile_compatible(physical_tile, &logical_block, capacity)) {
+                    compatible_sub_tiles.push_back(capacity);
+                }
+            }
+
+            compressed_block_grid.compatible_sub_tiles_map.insert({physical_tile->index, compatible_sub_tiles});
+        }
+
+        compressed_type_grids[logical_block.index] = compressed_block_grid;
     }
 
     return compressed_type_grids;

vpr/src/place/compressed_grid.h

@@ -32,6 +32,8 @@ struct t_compressed_block_grid {
     //stored sparsely, since we may not have full columns of blocks.
     //This makes it easy to check whether there exist
     std::vector<vtr::flat_map2<int, t_type_loc>> grid;
+
+    std::unordered_map<int, std::vector<int>> compatible_sub_tiles_map;
 };
 
 //Compressed grid space for each block type

vpr/src/place/move_utils.cpp

@@ -445,7 +445,7 @@ bool is_legal_swap_to_location(ClusterBlockId blk, t_pl_loc to) {
     auto logical_block = cluster_ctx.clb_nlist.block_type(blk);
 
     if (to.sub_tile < 0 || to.sub_tile >= physical_tile->capacity
-        || !is_tile_compatible(physical_tile, logical_block, to)) {
+        || !is_tile_compatible(physical_tile, logical_block, to.sub_tile)) {
         return false;
     }
     // If the destination block is user constrained, abort this swap
@@ -639,14 +639,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type,
 
     //Each x/y location possibly contains multiple sub tiles, so we need to pick
     //a z location within a compatible sub tile.
-    std::vector<int> compatible_sub_tiles;
-    for (int capacity = 0; capacity < to_type->capacity; capacity++) {
-        t_pl_loc loc(to.x, to.y, capacity);
-
-        if (is_tile_compatible(to_type, type, loc)) {
-            compatible_sub_tiles.push_back(capacity);
-        }
-    }
+    auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tiles_map.at(to_type->index);
     to.sub_tile = compatible_sub_tiles[vtr::irand((int)compatible_sub_tiles.size() - 1)];
 
     VTR_ASSERT_MSG(is_tile_compatible(to_type, type), "Type must be compatible");

vpr/src/route/route_common.cpp

@@ -848,8 +848,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
         auto type = physical_tile_type(blk_id);
         auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
 
-        int class_low, class_high;
-        get_class_range_for_block(blk_id, &class_low, &class_high);
+        auto class_range = get_class_range_for_block(blk_id);
 
         clb_opins_used_locally[blk_id].resize((int)type->class_inf.size());
 
@@ -873,7 +872,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
                     VTR_ASSERT(type->class_inf[iclass].type == DRIVER);
 
                     /* Check to make sure class is in same range as that assigned to block */
-                    VTR_ASSERT(iclass >= class_low && iclass <= class_high);
+                    VTR_ASSERT(iclass >= class_range.low && iclass <= class_range.high);
 
                     //We push back OPEN to reserve space to store the exact pin which
                     //will be reserved (determined later)
@@ -1030,12 +1029,11 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t
         auto type = physical_tile_type(blk_id);
         auto sub_tile = type->sub_tiles[get_sub_tile_index(blk_id)];
 
-        int class_low, class_high;
-        get_class_range_for_block(blk_id, &class_low, &class_high);
+        auto class_range = get_class_range_for_block(blk_id);
 
         rr_blk_source[blk_id].resize((int)type->class_inf.size());
         for (iclass = 0; iclass < (int)type->class_inf.size(); iclass++) {
-            if (iclass >= class_low && iclass <= class_high) {
+            if (iclass >= class_range.low && iclass <= class_range.high) {
                 i = place_ctx.block_locs[blk_id].loc.x;
                 j = place_ctx.block_locs[blk_id].loc.y;
 

vpr/src/route/rr_graph.cpp

@@ -1397,9 +1397,9 @@ static void build_rr_sinks_sources(const int i,
 
     auto type = grid[i][j].type;
     int num_class = (int)type->class_inf.size();
-    std::vector<t_class> class_inf = type->class_inf;
+    const std::vector<t_class>& class_inf = type->class_inf;
     int num_pins = type->num_pins;
-    std::vector<int> pin_class = type->pin_class;
+    const std::vector<int>& pin_class = type->pin_class;
 
     /* SINK and SOURCE-to-OPIN edges */
     for (int iclass = 0; iclass < num_class; ++iclass) {

vpr/src/route/rr_graph2.cpp

@@ -1454,7 +1454,7 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
      * and ptc gives the number of this resource.  ptc is the class number,
      * pin number or track number, depending on what type of resource this
      * is.  All ptcs start at 0 and go up to pins_per_clb-1 or the equivalent.
-     * There are (int)type->class_inf.size() SOURCEs + SINKs, type->num_pins IPINs + OPINs,
+     * There are class_inf size SOURCEs + SINKs, type->num_pins IPINs + OPINs,
      * and max_chan_width CHANX and CHANY (each).
      *
      * Note that for segments (CHANX and CHANY) of length > 1, the segment is

vpr/src/util/vpr_utils.cpp

@@ -726,9 +726,7 @@ int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node) {
     }
 }
 
-void get_class_range_for_block(const ClusterBlockId blk_id,
-                               int* class_low,
-                               int* class_high) {
+t_class_range get_class_range_for_block(const ClusterBlockId blk_id) {
     /* Assumes that the placement has been done so each block has a set of pins allocated to it */
     auto& place_ctx = g_vpr_ctx.placement();
 
@@ -741,8 +739,11 @@ void get_class_range_for_block(const ClusterBlockId blk_id,
     VTR_ASSERT((class_range_total) % sub_tile_capacity == 0);
     int rel_capacity = place_ctx.block_locs[blk_id].loc.sub_tile - sub_tile.capacity.low;
 
-    *class_low = rel_capacity * (class_range_total / sub_tile_capacity) + class_range.low;
-    *class_high = (rel_capacity + 1) * (class_range_total / sub_tile_capacity) - 1 + class_range.low;
+    t_class_range abs_class_range;
+    abs_class_range.low = rel_capacity * (class_range_total / sub_tile_capacity) + class_range.low;
+    abs_class_range.high = (rel_capacity + 1) * (class_range_total / sub_tile_capacity) - 1 + class_range.low;
+
+    return abs_class_range;
 }
 
 void get_pin_range_for_block(const ClusterBlockId blk_id,
@@ -2161,10 +2162,10 @@ bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_
     return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end();
 }
 
-bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, t_pl_loc loc) {
+bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc) {
     bool capacity_compatible = false;
     for (auto& sub_tile : physical_tile->sub_tiles) {
-        if (sub_tile.capacity.is_in_range(loc.sub_tile)) {
+        if (sub_tile.capacity.is_in_range(sub_tile_loc)) {
             capacity_compatible = true;
             break;
         }
@@ -2251,31 +2252,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
 
     VTR_ASSERT(sub_tile_index != OPEN);
 
-    t_logical_pin logical_pin(sub_tile_index, pin);
-
-    const auto& direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
-    auto result = direct_map.find(logical_pin);
-
-    if (result == direct_map.end()) {
-        VTR_LOG_WARN(
-            "Couldn't find the corresponding physical pin of the logical pin %d."
-            "Physical Tile: %s, Logical Block: %s.\n",
-            pin, physical_tile->name, logical_block->name);
-        return OPEN;
-    }
-
-    return result->second.pin;
-}
-
-int get_physical_pin_offset(t_sub_tile* sub_tile,
-                            t_physical_tile_type_ptr physical_tile) {
-    int offset = 0;
-
-    for (int isub_tile = 0; isub_tile < sub_tile->index; isub_tile++) {
-        offset += physical_tile->sub_tiles[isub_tile].num_phy_pins;
-    }
-
-    return offset;
+    return get_physical_pin(sub_tile_index, physical_tile, logical_block, pin);
 }
 
 int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) {

vpr/src/util/vpr_utils.h

@@ -35,9 +35,7 @@ int get_sub_tile_index(ClusterBlockId blk);
 
 int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node);
 
-void get_class_range_for_block(const ClusterBlockId blk_id,
-                               int* class_low,
-                               int* class_high);
+t_class_range get_class_range_for_block(const ClusterBlockId blk_id);
 
 void get_pin_range_for_block(const ClusterBlockId blk_id,
                              int* pin_low,
@@ -148,7 +146,7 @@ int get_max_num_pins(t_logical_block_type_ptr logical_block);
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);
 
-bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, t_pl_loc loc);
+bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc);
 
 //Returns the physical tile type which 'best' matches logical_block
 t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block);
@@ -170,8 +168,6 @@ int get_physical_pin(int sub_tile_index,
                      t_physical_tile_type_ptr physical_tile,
                      t_logical_block_type_ptr logical_block,
                      int pin);
-int get_physical_pin_offset(t_sub_tile* sub_tile,
-                            t_physical_tile_type_ptr physical_tile);
 
 //Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index
 int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index);