Updates based on the review

instead of going to random placement, going to neighbour placement if no available subtile found
minor optimization on available subtile vector and other style updates
updated QoR for vtr_reg_strong(_odin) based on above placement behaviour

Author: haydar-c

vpr/src/place/initial_placement.cpp

@@ -157,8 +157,11 @@ static bool is_loc_legal(const t_pl_loc& loc,
  *   @param pr The PartitionRegion of the macro head member - represents its floorplanning constraints, is the size of
  *   the whole chip if the macro is not constrained.
  *   @param rng A random number generator to select subtile from available and compatible ones.
+ *
+ * @return False if location on chip, legal, but no available subtile found. True otherwise. False leads us to
+ * neighbour placement currently. 
  */
-static void find_subtile_in_location(t_pl_loc& centroid, 
+static bool find_subtile_in_location(t_pl_loc& centroid, 
                              t_logical_block_type_ptr block_type,
                              const BlkLocRegistry& blk_loc_registry,
                              const PartitionRegion& pr,
@@ -176,10 +179,7 @@ static void find_subtile_in_location(t_pl_loc& centroid,
  */
 static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
                                                      t_pl_loc& centroid,
-                                                     const BlkLocRegistry& blk_loc_registry,
-                                                     t_logical_block_type_ptr block_type,
-                                                     const PartitionRegion& pr,
-                                                     vtr::RngContainer& rng);
+                                                     const BlkLocRegistry& blk_loc_registry);
 
 /**
  * @brief  Tries to find a nearest location to the centroid location if calculated centroid location is not legal or is occupied.
@@ -359,36 +359,41 @@ static bool is_loc_legal(const t_pl_loc& loc,
     return legal;
 }
 
-void find_subtile_in_location(t_pl_loc& centroid, 
+bool find_subtile_in_location(t_pl_loc& centroid, 
                              t_logical_block_type_ptr block_type,
                              const BlkLocRegistry& blk_loc_registry,
                              const PartitionRegion& pr,
                              vtr::RngContainer& rng) {
     //check if the location is on chip and legal, if yes try to update subtile
     if (is_loc_on_chip({centroid.x, centroid.y, centroid.layer}) &&  is_loc_legal(centroid, pr, block_type)) {
         //finding the subtile location
-        auto& device_ctx = g_vpr_ctx.device();
+        const auto& device_ctx = g_vpr_ctx.device();
         const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index];
         const auto& type = device_ctx.grid.get_physical_type({centroid.x, centroid.y, centroid.layer});
         const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index);
 
         //filter out occupied subtiles
         const GridBlock& grid_blocks = blk_loc_registry.grid_blocks();
         std::vector<int> available_sub_tiles;
+        available_sub_tiles.reserve(compatible_sub_tiles.size());
         for (int sub_tile : compatible_sub_tiles) {
             t_pl_loc pos = {centroid.x, centroid.y, sub_tile, centroid.layer};
             if (!grid_blocks.block_at_location(pos)) {
                 available_sub_tiles.push_back(sub_tile);
             }
         }
 
-        //if there is at least one available subtile, update the centroid and do not change otherwise
+        //If there is at least one available subtile, update the centroid. Otherwise, sincel location
+        //is legal and on chip but no subtile found, return false for trying neighbour placement.
         if (!available_sub_tiles.empty()) {
             centroid.sub_tile = available_sub_tiles[rng.irand((int)available_sub_tiles.size() - 1)];
+        } else {
+            return false;
         }
     }
-}
 
+    return true;
+}
 
 static bool find_centroid_neighbor(t_pl_loc& centroid_loc,
                                    t_logical_block_type_ptr block_type,
@@ -443,10 +448,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc,
 
 static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
                                                      t_pl_loc& centroid,
-                                                     const BlkLocRegistry& blk_loc_registry,
-                                                     t_logical_block_type_ptr block_type,
-                                                     const PartitionRegion& pr,
-                                                     vtr::RngContainer& rng) {
+                                                     const BlkLocRegistry& blk_loc_registry) {
     const auto& cluster_ctx = g_vpr_ctx.clustering();
     const auto& block_locs = blk_loc_registry.block_locs();
 
@@ -539,8 +541,6 @@ static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
         } else {
             centroid.layer = head_layer_num;
         }
-        //try to find an available and compatible subtile in that location
-        find_subtile_in_location(centroid, block_type, blk_loc_registry, pr, rng);
     }
 
     return connected_blocks_to_update;
@@ -606,10 +606,15 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
     t_pl_loc centroid_loc(OPEN, OPEN, OPEN, OPEN);
     std::vector<ClusterBlockId> unplaced_blocks_to_update_their_score;
 
+    bool try_neighbour_due_to_subtile = false;
+
     if (!flat_placement_info.valid) {
         // If a flat placement is not provided, use the centroid of connected
         // blocks which have already been placed.
-        unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry, block_type, pr, rng);
+        unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
+        if(!find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
+            try_neighbour_due_to_subtile = true;
+        }
     } else {
         // If a flat placement is provided, use the flat placement to get the
         // centroid.
@@ -621,7 +626,10 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
         //       location near the flat placement centroid.
         if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer}) ||
             !is_loc_legal(centroid_loc, pr, block_type)) {
-            unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry, block_type, pr, rng);
+            unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
+            if(!find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
+                try_neighbour_due_to_subtile = true;
+            }
         }
     }
 
@@ -632,9 +640,8 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
 
     //centroid suggestion was either occupied or does not match block type
     //try to find a near location that meet these requirements
-    bool neighbor_legal_loc = false;
-    if (!is_loc_legal(centroid_loc, pr, block_type)) {
-        neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, blk_loc_registry, rng);
+    if (!is_loc_legal(centroid_loc, pr, block_type) || try_neighbour_due_to_subtile) {
+        bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, blk_loc_registry, rng);
         if (!neighbor_legal_loc) { //no neighbor candidate found
             return false;
         }

vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt

@@ -1,5 +1,5 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- fixed_k6_frac_N8_22nm.xml	  single_wire.v	  common	  2.21	  vpr	  74.33 MiB	  	  -1	  -1	  0.11	  20252	  1	  0.04	  -1	  -1	  33084	  -1	  -1	  0	  1	  0	  0	  success	  v8.0.0-12161-g489698f01-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-18T11:17:37	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  76116	  1	  1	  0	  2	  0	  1	  2	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  2	  3	  0	  0	  3	  74.3 MiB	  0.69	  0.00	  0.2714	  -0.2714	  -0.2714	  nan	  0.43	  1.0929e-05	  6.519e-06	  7.2568e-05	  4.7472e-05	  74.3 MiB	  0.69	  74.3 MiB	  0.65	  8	  16	  1	  6.79088e+06	  0	  166176.	  575.005	  0.22	  0.00158287	  0.00149989	  20206	  45088	  -1	  18	  1	  1	  1	  141	  56	  0.7726	  nan	  -0.7726	  -0.7726	  0	  0	  202963.	  702.294	  0.02	  0.00	  0.05	  -1	  -1	  0.02	  0.00154764	  0.00146817	 
- fixed_k6_frac_N8_22nm.xml	  single_ff.v	  common	  2.52	  vpr	  74.56 MiB	  	  -1	  -1	  0.11	  20760	  1	  0.05	  -1	  -1	  33204	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-12161-g489698f01-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-18T11:17:37	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  76348	  2	  1	  3	  3	  1	  3	  4	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  22	  9	  3	  1	  5	  74.6 MiB	  0.80	  0.00	  0.74674	  -1.4524	  -0.74674	  0.74674	  0.51	  1.5909e-05	  9.307e-06	  0.000116047	  8.3478e-05	  74.6 MiB	  0.80	  74.6 MiB	  0.79	  20	  27	  1	  6.79088e+06	  13472	  414966.	  1435.87	  0.34	  0.0016991	  0.00160343	  22510	  95286	  -1	  26	  1	  2	  2	  102	  24	  0.691615	  0.691615	  -1.31306	  -0.691615	  0	  0	  503264.	  1741.40	  0.07	  0.00	  0.10	  -1	  -1	  0.07	  0.00163206	  0.00154606	 
- fixed_k6_frac_N8_22nm.xml	  ch_intrinsics.v	  common	  4.24	  vpr	  74.95 MiB	  	  -1	  -1	  0.40	  21656	  3	  0.11	  -1	  -1	  37052	  -1	  -1	  32	  99	  1	  0	  success	  v8.0.0-12161-g489698f01-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-18T11:17:37	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  76744	  99	  130	  240	  229	  1	  229	  262	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  883	  19536	  1068	  3887	  14581	  74.9 MiB	  0.98	  0.00	  1.86512	  -124.45	  -1.86512	  1.86512	  0.46	  0.000779688	  0.000721122	  0.0213475	  0.0197246	  74.9 MiB	  0.98	  74.9 MiB	  0.96	  32	  1890	  11	  6.79088e+06	  979104	  586450.	  2029.24	  0.75	  0.142133	  0.121646	  24814	  144142	  -1	  1712	  13	  543	  802	  57386	  17520	  1.9213	  1.9213	  -143.517	  -1.9213	  -0.04337	  -0.04337	  744469.	  2576.02	  0.05	  0.07	  0.20	  -1	  -1	  0.05	  0.066598	  0.0611661	 
- fixed_k6_frac_N8_22nm.xml	  diffeq1.v	  common	  21.52	  vpr	  76.91 MiB	  	  -1	  -1	  0.62	  26520	  15	  0.62	  -1	  -1	  38216	  -1	  -1	  47	  162	  0	  5	  success	  v8.0.0-12161-g489698f01-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-18T11:17:37	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  78760	  162	  96	  817	  258	  1	  740	  310	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  7006	  24414	  236	  6771	  17407	  76.9 MiB	  2.93	  0.01	  21.8698	  -1649.28	  -21.8698	  21.8698	  0.59	  0.00295868	  0.00276614	  0.109664	  0.102635	  76.9 MiB	  2.93	  76.9 MiB	  1.51	  60	  14847	  46	  6.79088e+06	  2.61318e+06	  1.01997e+06	  3529.29	  13.54	  1.39808	  1.28894	  29998	  257685	  -1	  12402	  16	  3793	  9643	  1173029	  292327	  21.3427	  21.3427	  -1635.12	  -21.3427	  0	  0	  1.27783e+06	  4421.56	  0.08	  0.35	  0.26	  -1	  -1	  0.08	  0.183513	  0.17225	 
+ fixed_k6_frac_N8_22nm.xml	  single_wire.v	  common	  2.25	  vpr	  75.57 MiB	  	  -1	  -1	  0.11	  20616	  1	  0.02	  -1	  -1	  33172	  -1	  -1	  0	  1	  0	  0	  success	  v8.0.0-12163-g0dba7016b-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-19T17:54:19	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  77384	  1	  1	  0	  2	  0	  1	  2	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  2	  3	  0	  0	  3	  75.6 MiB	  0.82	  0.00	  0.2714	  -0.2714	  -0.2714	  nan	  0.60	  1.0195e-05	  5.861e-06	  7.0627e-05	  4.5591e-05	  75.6 MiB	  0.82	  75.6 MiB	  0.78	  8	  16	  1	  6.79088e+06	  0	  166176.	  575.005	  0.22	  0.0015764	  0.00149137	  20206	  45088	  -1	  18	  1	  1	  1	  141	  56	  0.7726	  nan	  -0.7726	  -0.7726	  0	  0	  202963.	  702.294	  0.02	  0.00	  0.06	  -1	  -1	  0.02	  0.00154357	  0.00147507	 
+ fixed_k6_frac_N8_22nm.xml	  single_ff.v	  common	  2.07	  vpr	  75.57 MiB	  	  -1	  -1	  0.11	  21004	  1	  0.02	  -1	  -1	  33328	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-12163-g0dba7016b-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-19T17:54:19	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  77388	  2	  1	  3	  3	  1	  3	  4	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  22	  9	  3	  1	  5	  75.6 MiB	  0.70	  0.00	  0.74674	  -1.4524	  -0.74674	  0.74674	  0.55	  1.7604e-05	  1.0829e-05	  0.000109132	  7.4428e-05	  75.6 MiB	  0.70	  75.6 MiB	  0.69	  20	  27	  1	  6.79088e+06	  13472	  414966.	  1435.87	  0.36	  0.00134255	  0.00124027	  22510	  95286	  -1	  26	  1	  2	  2	  102	  24	  0.691615	  0.691615	  -1.31306	  -0.691615	  0	  0	  503264.	  1741.40	  0.04	  0.00	  0.12	  -1	  -1	  0.04	  0.00165403	  0.00156635	 
+ fixed_k6_frac_N8_22nm.xml	  ch_intrinsics.v	  common	  2.78	  vpr	  76.11 MiB	  	  -1	  -1	  0.25	  22288	  3	  0.07	  -1	  -1	  36924	  -1	  -1	  32	  99	  1	  0	  success	  v8.0.0-12163-g0dba7016b-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-19T17:54:19	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  77936	  99	  130	  240	  229	  1	  229	  262	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  883	  19536	  1068	  3887	  14581	  76.1 MiB	  0.67	  0.00	  1.86512	  -124.45	  -1.86512	  1.86512	  0.39	  0.000560506	  0.000504742	  0.0161729	  0.0146716	  76.1 MiB	  0.67	  76.1 MiB	  0.66	  32	  1890	  11	  6.79088e+06	  979104	  586450.	  2029.24	  0.47	  0.0893208	  0.0810973	  24814	  144142	  -1	  1712	  13	  543	  802	  57386	  17520	  1.9213	  1.9213	  -143.517	  -1.9213	  -0.04337	  -0.04337	  744469.	  2576.02	  0.06	  0.05	  0.19	  -1	  -1	  0.06	  0.053443	  0.048647	 
+ fixed_k6_frac_N8_22nm.xml	  diffeq1.v	  common	  12.29	  vpr	  77.89 MiB	  	  -1	  -1	  0.61	  27152	  15	  0.49	  -1	  -1	  38004	  -1	  -1	  47	  162	  0	  5	  success	  v8.0.0-12163-g0dba7016b-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-19T17:54:19	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  79760	  162	  96	  817	  258	  1	  740	  310	  17	  17	  289	  -1	  unnamed_device	  -1	  -1	  7006	  24414	  236	  6771	  17407	  77.9 MiB	  1.84	  0.01	  21.8698	  -1649.28	  -21.8698	  21.8698	  0.44	  0.00183251	  0.0016749	  0.0693904	  0.0634239	  77.9 MiB	  1.84	  77.9 MiB	  1.10	  60	  14847	  46	  6.79088e+06	  2.61318e+06	  1.01997e+06	  3529.29	  6.71	  1.05045	  0.971299	  29998	  257685	  -1	  12402	  16	  3793	  9643	  1173029	  292327	  21.3427	  21.3427	  -1635.12	  -21.3427	  0	  0	  1.27783e+06	  4421.56	  0.06	  0.28	  0.21	  -1	  -1	  0.06	  0.146101	  0.135935