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acomodiacomodi
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Updated all test architectures with the upgrade_arch script
Signed-off-by: Alessandro Comodi <[email protected]>
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‎libs/libarchfpga/arch/mult_luts_arch.xml

Lines changed: 620 additions & 605 deletions
Large diffs are not rendered by default.

‎libs/libarchfpga/arch/sample_arch.xml

Lines changed: 129 additions & 137 deletions
Large diffs are not rendered by default.

‎utils/fasm/test/test_fasm_arch.xml

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,27 @@
11
<architecture>
2-
<models/>
2+
<models/><tiles><tile name="io" capacity="8"><equivalent_sites><site pb_type="io"/></equivalent_sites><input name="outpad" num_pins="1"/>
3+
<output name="inpad" num_pins="1"/>
4+
<clock name="clock" num_pins="1"/>
5+
6+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
7+
8+
<pinlocations pattern="custom">
9+
<loc side="left">io.outpad io.inpad io.clock</loc>
10+
<loc side="top">io.outpad io.inpad io.clock</loc>
11+
<loc side="right">io.outpad io.inpad io.clock</loc>
12+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
13+
</pinlocations>
14+
15+
</tile><tile name="clb"><equivalent_sites><site pb_type="clb"/></equivalent_sites><input name="I" num_pins="33" equivalent="full"/>
16+
<output name="O" num_pins="20" equivalent="none"/>
17+
<clock name="clk" num_pins="1"/>
18+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
19+
20+
<pinlocations pattern="spread"/>
21+
</tile></tiles>
322

423
<layout>
5-
<fixed_layout height="10" width="10" name="test" >
24+
<fixed_layout height="10" width="10" name="test">
625
<perimeter type="io" priority="100">
726
<metadata>
827
<meta name="type">io</meta>
@@ -42,7 +61,7 @@
4261
</segmentlist>
4362

4463
<complexblocklist>
45-
<pb_type name="io" capacity="8">
64+
<pb_type name="io">
4665
<input name="outpad" num_pins="1"/>
4766
<output name="inpad" num_pins="1"/>
4867
<clock name="clock" num_pins="1"/>
@@ -76,19 +95,10 @@
7695
</mode>
7796

7897
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
79-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
80-
8198
<!-- IOs go on the periphery of the FPGA, for consistency,
8299
make it physically equivalent on all sides so that only one definition of I/Os is needed.
83100
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
84101
-->
85-
<pinlocations pattern="custom">
86-
<loc side="left">io.outpad io.inpad io.clock</loc>
87-
<loc side="top">io.outpad io.inpad io.clock</loc>
88-
<loc side="right">io.outpad io.inpad io.clock</loc>
89-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
90-
</pinlocations>
91-
92102
<!-- Place I/Os on the sides of the FPGA -->
93103
<power method="ignore"/>
94104
</pb_type>
@@ -258,15 +268,12 @@
258268
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
259269
</interconnect>
260270

261-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
262-
263-
<pinlocations pattern="spread"/>
264-
</pb_type>
271+
</pb_type>
265272
</complexblocklist>
266273
<power>
267274
<local_interconnect C_wire="2.5e-10"/>
268275
</power>
269276
<clocks>
270277
<clock buffer_size="auto" C_wire="2.5e-10"/>
271278
</clocks>
272-
</architecture>
279+
</architecture>

‎vpr/test/test_read_arch_metadata.xml

Lines changed: 23 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,24 @@
11
<architecture>
2-
<models/>
2+
<models/><tiles><tile name="io" capacity="8"><equivalent_sites><site pb_type="io"/></equivalent_sites><input name="outpad" num_pins="1"/>
3+
<output name="inpad" num_pins="1"/>
4+
<clock name="clock" num_pins="1"/>
5+
6+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
7+
8+
<pinlocations pattern="custom">
9+
<loc side="left">io.outpad io.inpad io.clock</loc>
10+
<loc side="top">io.outpad io.inpad io.clock</loc>
11+
<loc side="right">io.outpad io.inpad io.clock</loc>
12+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
13+
</pinlocations>
14+
15+
</tile><tile name="clb"><equivalent_sites><site pb_type="clb"/></equivalent_sites><input name="I" num_pins="33" equivalent="full"/>
16+
<output name="O" num_pins="20" equivalent="none"/>
17+
<clock name="clk" num_pins="1"/>
18+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
19+
20+
<pinlocations pattern="spread"/>
21+
</tile></tiles>
322

423
<layout>
524
<auto_layout aspect_ratio="1.0">
@@ -43,7 +62,7 @@
4362
</segmentlist>
4463

4564
<complexblocklist>
46-
<pb_type name="io" capacity="8">
65+
<pb_type name="io">
4766
<metadata>
4867
<meta name="pb_type_type">pb_type = io</meta>
4968
</metadata>
@@ -80,19 +99,10 @@
8099
</mode>
81100

82101
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
83-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
84-
85102
<!-- IOs go on the periphery of the FPGA, for consistency,
86103
make it physically equivalent on all sides so that only one definition of I/Os is needed.
87104
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
88105
-->
89-
<pinlocations pattern="custom">
90-
<loc side="left">io.outpad io.inpad io.clock</loc>
91-
<loc side="top">io.outpad io.inpad io.clock</loc>
92-
<loc side="right">io.outpad io.inpad io.clock</loc>
93-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
94-
</pinlocations>
95-
96106
<!-- Place I/Os on the sides of the FPGA -->
97107
<power method="ignore"/>
98108
</pb_type>
@@ -222,15 +232,12 @@
222232
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
223233
</interconnect>
224234

225-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
226-
227-
<pinlocations pattern="spread"/>
228-
</pb_type>
235+
</pb_type>
229236
</complexblocklist>
230237
<power>
231238
<local_interconnect C_wire="2.5e-10"/>
232239
</power>
233240
<clocks>
234241
<clock buffer_size="auto" C_wire="2.5e-10"/>
235242
</clocks>
236-
</architecture>
243+
</architecture>

‎vtr_flow/arch/bidir/k4_n4_v7_bidir.xml

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,27 @@ Architecture based off Stratix IV
2222

2323
<!-- ODIN II specific config -->
2424
<models>
25-
</models>
25+
</models><tiles><tile name="io" capacity="4"><equivalent_sites><site pb_type="io"/></equivalent_sites><input name="outpad" num_pins="1"/>
26+
<output name="inpad" num_pins="1"/>
27+
<clock name="clock" num_pins="1"/>
28+
29+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
30+
31+
<pinlocations pattern="custom">
32+
<loc side="left">io.outpad io.inpad io.clock</loc>
33+
<loc side="top">io.outpad io.inpad io.clock</loc>
34+
<loc side="right">io.outpad io.inpad io.clock</loc>
35+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
36+
</pinlocations>
37+
38+
</tile><tile name="clb"><equivalent_sites><site pb_type="clb"/></equivalent_sites><input name="I" num_pins="10" equivalent="full"/>
39+
<output name="O" num_pins="4" equivalent="instance"/>
40+
<clock name="clk" num_pins="1"/>
41+
42+
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
43+
44+
<pinlocations pattern="spread"/>
45+
</tile></tiles>
2646
<!-- ODIN II specific config ends -->
2747

2848
<!-- Physical descriptions begin (area optimized for N10-K6-L4) -->
@@ -62,7 +82,7 @@ Architecture based off Stratix IV
6282

6383
<complexblocklist>
6484
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
65-
<pb_type name="io" capacity="4">
85+
<pb_type name="io">
6686
<input name="outpad" num_pins="1"/>
6787
<output name="inpad" num_pins="1"/>
6888
<clock name="clock" num_pins="1"/>
@@ -90,19 +110,10 @@ Architecture based off Stratix IV
90110
</interconnect>
91111
</mode>
92112

93-
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
94-
95113
<!-- IOs go on the periphery of the FPGA, for consistency,
96114
make it physically equivalent on all sides so that only one definition of I/Os is needed.
97115
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
98116
-->
99-
<pinlocations pattern="custom">
100-
<loc side="left">io.outpad io.inpad io.clock</loc>
101-
<loc side="top">io.outpad io.inpad io.clock</loc>
102-
<loc side="right">io.outpad io.inpad io.clock</loc>
103-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
104-
</pinlocations>
105-
106117
</pb_type>
107118

108119

@@ -169,9 +180,6 @@ Architecture based off Stratix IV
169180
</interconnect>
170181

171182

172-
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
173-
174-
<pinlocations pattern="spread"/>
175183
</pb_type>
176184

177185
</complexblocklist>

‎vtr_flow/arch/bidir/k4_n4_v7_bidir_pass_gate.xml

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,27 @@ Architecture based off Stratix IV
2222

2323
<!-- ODIN II specific config -->
2424
<models>
25-
</models>
25+
</models><tiles><tile name="io" capacity="4"><equivalent_sites><site pb_type="io"/></equivalent_sites><input name="outpad" num_pins="1"/>
26+
<output name="inpad" num_pins="1"/>
27+
<clock name="clock" num_pins="1"/>
28+
29+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
30+
31+
<pinlocations pattern="custom">
32+
<loc side="left">io.outpad io.inpad io.clock</loc>
33+
<loc side="top">io.outpad io.inpad io.clock</loc>
34+
<loc side="right">io.outpad io.inpad io.clock</loc>
35+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
36+
</pinlocations>
37+
38+
</tile><tile name="clb"><equivalent_sites><site pb_type="clb"/></equivalent_sites><input name="I" num_pins="10" equivalent="full"/>
39+
<output name="O" num_pins="4" equivalent="instance"/>
40+
<clock name="clk" num_pins="1"/>
41+
42+
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
43+
44+
<pinlocations pattern="spread"/>
45+
</tile></tiles>
2646
<!-- ODIN II specific config ends -->
2747

2848
<!-- Physical descriptions begin (area optimized for N10-K6-L4) -->
@@ -63,7 +83,7 @@ Architecture based off Stratix IV
6383

6484
<complexblocklist>
6585
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
66-
<pb_type name="io" capacity="4">
86+
<pb_type name="io">
6787
<input name="outpad" num_pins="1"/>
6888
<output name="inpad" num_pins="1"/>
6989
<clock name="clock" num_pins="1"/>
@@ -91,19 +111,10 @@ Architecture based off Stratix IV
91111
</interconnect>
92112
</mode>
93113

94-
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
95-
96114
<!-- IOs go on the periphery of the FPGA, for consistency,
97115
make it physically equivalent on all sides so that only one definition of I/Os is needed.
98116
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
99117
-->
100-
<pinlocations pattern="custom">
101-
<loc side="left">io.outpad io.inpad io.clock</loc>
102-
<loc side="top">io.outpad io.inpad io.clock</loc>
103-
<loc side="right">io.outpad io.inpad io.clock</loc>
104-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
105-
</pinlocations>
106-
107118
</pb_type>
108119

109120

@@ -170,9 +181,6 @@ Architecture based off Stratix IV
170181
</interconnect>
171182

172183

173-
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
174-
175-
<pinlocations pattern="spread"/>
176184
</pb_type>
177185

178186
</complexblocklist>

‎vtr_flow/arch/bidir/k4_n4_v7_l1_bidir.xml

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,27 @@ Architecture based off Stratix IV
2222

2323
<!-- ODIN II specific config -->
2424
<models>
25-
</models>
25+
</models><tiles><tile name="io" capacity="4"><equivalent_sites><site pb_type="io"/></equivalent_sites><input name="outpad" num_pins="1"/>
26+
<output name="inpad" num_pins="1"/>
27+
<clock name="clock" num_pins="1"/>
28+
29+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
30+
31+
<pinlocations pattern="custom">
32+
<loc side="left">io.outpad io.inpad io.clock</loc>
33+
<loc side="top">io.outpad io.inpad io.clock</loc>
34+
<loc side="right">io.outpad io.inpad io.clock</loc>
35+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
36+
</pinlocations>
37+
38+
</tile><tile name="clb"><equivalent_sites><site pb_type="clb"/></equivalent_sites><input name="I" num_pins="10" equivalent="full"/>
39+
<output name="O" num_pins="4" equivalent="instance"/>
40+
<clock name="clk" num_pins="1"/>
41+
42+
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
43+
44+
<pinlocations pattern="spread"/>
45+
</tile></tiles>
2646
<!-- ODIN II specific config ends -->
2747

2848
<!-- Physical descriptions begin (area optimized for N10-K6-L4) -->
@@ -62,7 +82,7 @@ Architecture based off Stratix IV
6282

6383
<complexblocklist>
6484
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
65-
<pb_type name="io" capacity="4">
85+
<pb_type name="io">
6686
<input name="outpad" num_pins="1"/>
6787
<output name="inpad" num_pins="1"/>
6888
<clock name="clock" num_pins="1"/>
@@ -90,19 +110,10 @@ Architecture based off Stratix IV
90110
</interconnect>
91111
</mode>
92112

93-
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
94-
95113
<!-- IOs go on the periphery of the FPGA, for consistency,
96114
make it physically equivalent on all sides so that only one definition of I/Os is needed.
97115
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
98116
-->
99-
<pinlocations pattern="custom">
100-
<loc side="left">io.outpad io.inpad io.clock</loc>
101-
<loc side="top">io.outpad io.inpad io.clock</loc>
102-
<loc side="right">io.outpad io.inpad io.clock</loc>
103-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
104-
</pinlocations>
105-
106117
</pb_type>
107118

108119

@@ -169,9 +180,6 @@ Architecture based off Stratix IV
169180
</interconnect>
170181

171182

172-
<fc in_type="frac" in_val="0.5" out_type="frac" out_val="0.25"/>
173-
174-
<pinlocations pattern="spread"/>
175183
</pb_type>
176184

177185
</complexblocklist>

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