@@ -110,7 +110,7 @@ TEST_CASE("read_interchange_tiles", "[vpr]") {
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FPGAInterchangeReadArch (kArchFile , /* timing_enabled=*/ true , &arch, physical_tile_types, logical_block_types);
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- std::unordered_set<std::string> ptypes = {" NULL " , " IOB" , " PWR" , " CLB" };
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+ std::unordered_set<std::string> ptypes = {" EMPTY " , " IOB" , " PWR" , " CLB" };
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// Check that there are exactly the expected models
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for (auto ptype : physical_tile_types) {
@@ -134,7 +134,7 @@ TEST_CASE("read_interchange_pb_types", "[vpr]") {
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FPGAInterchangeReadArch (kArchFile , /* timing_enabled=*/ true , &arch, physical_tile_types, logical_block_types);
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- std::unordered_set<std::string> ltypes = {" NULL " , " IOPAD" , " SLICE" , " POWER" };
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+ std::unordered_set<std::string> ltypes = {" EMPTY " , " IOPAD" , " SLICE" , " POWER" };
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std::unordered_map<std::string, PORTS> slice_ports = {
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{" L0_0" , PORTS::IN_PORT},
@@ -162,7 +162,7 @@ TEST_CASE("read_interchange_pb_types", "[vpr]") {
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ltypes.erase (name);
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if (ltype.pb_type == nullptr ) {
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- REQUIRE (name == std::string (" NULL " ));
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+ REQUIRE (name == std::string (" EMPTY " ));
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continue ;
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}
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