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vpr: base: netlist: fixed bottlneck when reading netlist
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent 2c45627 commit 44b094d

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+70
-68
lines changed

1 file changed

+70
-68
lines changed

vpr/src/base/read_interchange_netlist.cpp

Lines changed: 70 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ struct NetlistReader {
5757
outpad_model_ = find_model(MODEL_OUTPUT);
5858
main_netlist_.set_block_types(inpad_model_, outpad_model_);
5959

60+
prepare_port_net_maps();
61+
6062
VTR_LOG("Reading IOs...\n");
6163
read_ios();
6264
VTR_LOG("Reading names...\n");
@@ -78,6 +80,59 @@ struct NetlistReader {
7880

7981
LogicalNetlist::Netlist::CellInstance::Reader top_cell_instance_;
8082

83+
std::unordered_map<size_t, std::unordered_map<std::pair<size_t, size_t>, std::string, vtr::hash_pair>> port_net_maps_;
84+
85+
void prepare_port_net_maps() {
86+
auto inst_list = nr_.getInstList();
87+
auto decl_list = nr_.getCellDecls();
88+
auto str_list = nr_.getStrList();
89+
auto port_list = nr_.getPortList();
90+
auto top_cell = nr_.getCellList()[nr_.getTopInst().getCell()];
91+
92+
for (auto net : top_cell.getNets()) {
93+
std::string net_name = str_list[net.getName()];
94+
95+
// Rename constant nets to their correct name based on the device architecture
96+
// database
97+
for (auto port : net.getPortInsts()) {
98+
if (port.isExtPort())
99+
continue;
100+
101+
auto port_inst = port.getInst();
102+
auto cell = inst_list[port_inst].getCell();
103+
if (str_list[decl_list[cell].getName()] == arch_.gnd_cell.first)
104+
net_name = arch_.gnd_net;
105+
106+
if (str_list[decl_list[cell].getName()] == arch_.vcc_cell.first)
107+
net_name = arch_.vcc_net;
108+
}
109+
110+
for (auto port : net.getPortInsts()) {
111+
if (!port.isInst())
112+
continue;
113+
114+
size_t inst = port.getInst();
115+
116+
size_t port_bit = get_port_bit(port);
117+
118+
auto port_idx = port.getPort();
119+
int start, end;
120+
std::tie(start, end) = get_bus_range(port_list[port_idx]);
121+
122+
int bus_size = std::abs(end - start);
123+
124+
port_bit = start < end ? port_bit : bus_size - port_bit;
125+
126+
auto pair = std::make_pair(port_idx, port_bit);
127+
std::unordered_map<std::pair<size_t, size_t>, std::string, vtr::hash_pair> map{{pair, net_name}};
128+
129+
auto result = port_net_maps_.emplace(inst, map);
130+
if (!result.second)
131+
result.first->second.emplace(pair, net_name);
132+
}
133+
}
134+
}
135+
81136
void read_ios() {
82137
const t_model* input_model = find_model(MODEL_INPUT);
83138
const t_model* output_model = find_model(MODEL_OUTPUT);
@@ -141,7 +196,7 @@ struct NetlistReader {
141196
auto port_list = nr_.getPortList();
142197
auto str_list = nr_.getStrList();
143198

144-
std::vector<std::tuple<unsigned int, int, std::string>> insts;
199+
std::vector<std::tuple<size_t, int, std::string>> insts;
145200
for (auto cell_inst : top_cell.getInsts()) {
146201
auto cell = decl_list[inst_list[cell_inst].getCell()];
147202

@@ -150,12 +205,14 @@ struct NetlistReader {
150205
std::string init_param;
151206
std::tie(is_lut, width, init_param) = is_lut_cell(str_list[cell.getName()]);
152207

153-
if (is_lut)
154-
insts.emplace_back(cell_inst, width, init_param);
208+
if (!is_lut)
209+
continue;
210+
211+
insts.emplace_back(cell_inst, width, init_param);
155212
}
156213

157214
for (auto inst : insts) {
158-
unsigned int inst_idx;
215+
size_t inst_idx;
159216
int lut_width;
160217
std::string init_param;
161218
std::tie(inst_idx, lut_width, init_param) = inst;
@@ -260,24 +317,15 @@ struct NetlistReader {
260317
AtomPortId oport_id = main_netlist_.create_port(blk_id, blk_model->outputs);
261318

262319
auto cell_lib = decl_list[inst_list[inst_idx].getCell()];
263-
std::unordered_map<unsigned int, std::string> port_net_map;
264-
265-
for (auto net : top_cell.getNets()) {
266-
std::string net_name = str_list[net.getName()];
267-
for (auto port : net.getPortInsts()) {
268-
if (!port.isInst() || port.getInst() != inst_idx)
269-
continue;
270-
271-
port_net_map.emplace(port.getPort(), net_name);
272-
}
273-
}
274-
320+
auto port_net_map = port_net_maps_.at(inst_idx);
275321
int inum = 0;
276322
for (auto port : cell_lib.getPorts()) {
277-
if (port_net_map.find(port) == port_net_map.end())
323+
std::pair<size_t, size_t> pair{port, 0};
324+
325+
if (port_net_map.find(pair) == port_net_map.end())
278326
continue;
279327

280-
auto net_name = port_net_map.at(port);
328+
auto net_name = port_net_map.at(pair);
281329
AtomNetId net_id = main_netlist_.create_net(net_name);
282330

283331
auto dir = port_list[port].getDir();
@@ -303,7 +351,7 @@ struct NetlistReader {
303351
auto port_list = nr_.getPortList();
304352
auto str_list = nr_.getStrList();
305353

306-
std::vector<std::pair<unsigned int, unsigned int>> insts;
354+
std::vector<std::pair<size_t, size_t>> insts;
307355
for (auto cell_inst : top_cell.getInsts()) {
308356
auto cell = decl_list[inst_list[cell_inst].getCell()];
309357

@@ -334,7 +382,7 @@ struct NetlistReader {
334382
inst_name.c_str(), conflicting_model->name, blk_model->name);
335383
}
336384

337-
auto port_net_map = get_port_net_map(inst_idx);
385+
auto port_net_map = port_net_maps_.at(inst_idx);
338386

339387
auto cell = decl_list[inst_list[inst_idx].getCell()];
340388
if (str_list[cell.getName()] == arch_.vcc_cell.first)
@@ -445,60 +493,14 @@ struct NetlistReader {
445493
return std::make_pair(0, 0);
446494
}
447495

448-
unsigned int get_port_bit(LogicalNetlist::Netlist::PortInstance::Reader port_inst_reader) {
449-
unsigned int port_bit = 0;
496+
size_t get_port_bit(LogicalNetlist::Netlist::PortInstance::Reader port_inst_reader) {
497+
size_t port_bit = 0;
450498
if (port_inst_reader.getBusIdx().which() == LogicalNetlist::Netlist::PortInstance::BusIdx::IDX)
451499
port_bit = port_inst_reader.getBusIdx().getIdx();
452500

453501
return port_bit;
454502
}
455503

456-
std::unordered_map<std::pair<unsigned int, unsigned int>, std::string, vtr::hash_pair> get_port_net_map(unsigned int inst_idx) {
457-
auto inst_list = nr_.getInstList();
458-
auto decl_list = nr_.getCellDecls();
459-
auto str_list = nr_.getStrList();
460-
auto port_list = nr_.getPortList();
461-
462-
auto top_cell = nr_.getCellList()[nr_.getTopInst().getCell()];
463-
std::unordered_map<std::pair<unsigned int, unsigned int>, std::string, vtr::hash_pair> map;
464-
for (auto net : top_cell.getNets()) {
465-
std::string net_name = str_list[net.getName()];
466-
467-
for (auto port : net.getPortInsts()) {
468-
if (port.isExtPort())
469-
continue;
470-
471-
auto port_inst = port.getInst();
472-
auto cell = inst_list[port_inst].getCell();
473-
if (str_list[decl_list[cell].getName()] == arch_.gnd_cell.first)
474-
net_name = arch_.gnd_net;
475-
476-
if (str_list[decl_list[cell].getName()] == arch_.vcc_cell.first)
477-
net_name = arch_.vcc_net;
478-
}
479-
480-
for (auto port : net.getPortInsts()) {
481-
if (!port.isInst() || port.getInst() != inst_idx)
482-
continue;
483-
484-
unsigned int port_bit = get_port_bit(port);
485-
486-
auto port_idx = port.getPort();
487-
int start, end;
488-
std::tie(start, end) = get_bus_range(port_list[port_idx]);
489-
490-
int bus_size = std::abs(end - start);
491-
492-
port_bit = start < end ? port_bit : bus_size - port_bit;
493-
494-
auto pair = std::make_pair(port_idx, port_bit);
495-
map.emplace(pair, net_name);
496-
}
497-
}
498-
499-
return map;
500-
}
501-
502504
std::tuple<bool, int, std::string> is_lut_cell(std::string cell_name) {
503505
for (auto lut_cell : arch_.lut_cells) {
504506
if (cell_name == lut_cell.name) {

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