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tangxifantangxifan
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Merge pull request #1932 from ethanroj23/rr_graph_view_nodes
RRGraphView nodes() Implementation
2 parents c6e5a56 + c219313 commit 3b7cae7

18 files changed

+239
-212
lines changed

‎utils/fasm/test/test_fasm.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -254,12 +254,12 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
254254

255255
auto &device_ctx = g_vpr_ctx.mutable_device();
256256
const auto& rr_graph = device_ctx.rr_graph;
257-
for(size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
258-
for(t_edge_size iedge = 0; iedge < rr_graph.num_edges(RRNodeId(inode)); ++iedge) {
259-
auto sink_inode = size_t(rr_graph.edge_sink_node(RRNodeId(inode), iedge));
260-
auto switch_id = rr_graph.edge_switch(RRNodeId(inode), iedge);
257+
for (const RRNodeId& inode : rr_graph.nodes()){
258+
for(t_edge_size iedge = 0; iedge < rr_graph.num_edges(inode); ++iedge) {
259+
auto sink_inode = size_t(rr_graph.edge_sink_node(inode, iedge));
260+
auto switch_id = rr_graph.edge_switch(inode, iedge);
261261
auto value = vtr::string_fmt("%d_%d_%zu",
262-
inode, sink_inode, switch_id);
262+
(size_t)inode, sink_inode, switch_id);
263263

264264
// Add additional features to edges that go to CLB.I[11:0] pins
265265
// to correlate them with features of CLB input mux later.
@@ -269,7 +269,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
269269
value = value + "\n" + pin_feature;
270270
}
271271

272-
vpr::add_rr_edge_metadata(inode, sink_inode, switch_id,
272+
vpr::add_rr_edge_metadata((size_t)inode, sink_inode, switch_id,
273273
vtr::string_view("fasm_features"), vtr::string_view(value.data(), value.size()));
274274
}
275275
}

‎vpr/src/device/rr_graph_view.h

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,26 @@ class RRGraphView {
5555
* kind of accessors
5656
*/
5757
public:
58+
/* Aggregates: create range-based loops for nodes
59+
* To iterate over the nodes in a RRGraph,
60+
* using a range-based loop is suggested.
61+
* -----------------------------------------------------------------
62+
* Example: iterate over all the nodes
63+
* // Strongly suggest to use a read-only rr_graph object
64+
* const RRGraph& rr_graph;
65+
* for (const RRNodeId& node : rr_graph.nodes()) {
66+
* // Do something with each node
67+
* }
68+
*/
69+
inline vtr::StrongIdRange<RRNodeId> nodes() const {
70+
return vtr::StrongIdRange<RRNodeId>(RRNodeId(0), RRNodeId(size()));
71+
}
72+
73+
/** @brief Return number of nodes. This function is inlined for runtime optimization. */
74+
inline size_t size() const {
75+
return node_storage_.size();
76+
}
77+
5878
/** @brief Get the type of a routing resource node. This function is inlined for runtime optimization. */
5979
inline t_rr_type node_type(RRNodeId node) const {
6080
return node_storage_.node_type(node);
@@ -299,9 +319,17 @@ class RRGraphView {
299319
return node_storage_.non_configurable_edges(node);
300320
}
301321

302-
/** @brief Get ID range for edges. This function is inlined for runtime optimization. */
303-
inline edge_idx_range edges(RRNodeId node) const {
304-
return node_storage_.edges(node);
322+
/** @brief Get outgoing edges for a node.
323+
* This API is designed to enable range-based loop to walk through the outgoing edges of a node
324+
* Example:
325+
* RRGraphView rr_graph; // A dummny rr_graph for a short example
326+
* RRNodeId node; // A dummy node for a short example
327+
* for (RREdgeId edge : rr_graph.edges(node)) {
328+
* // Do something with the edge
329+
* }
330+
*/
331+
inline edge_idx_range edges(const RRNodeId& id) const {
332+
return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id)));
305333
}
306334

307335
/** @brief Get the number of edges. This function is inlined for runtime optimization. */

‎vpr/src/draw/draw.cpp

Lines changed: 45 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -973,6 +973,7 @@ void init_draw_coords(float width_val) {
973973
t_draw_state* draw_state = get_draw_state_vars();
974974
t_draw_coords* draw_coords = get_draw_coords_vars();
975975
auto& device_ctx = g_vpr_ctx.device();
976+
const auto& rr_graph = device_ctx.rr_graph;
976977

977978
if (!draw_state->show_graphics && !draw_state->save_graphics
978979
&& draw_state->graphics_commands.empty())
@@ -983,9 +984,10 @@ void init_draw_coords(float width_val) {
983984
draw_state->draw_rr_node = (t_draw_rr_node*)vtr::realloc(
984985
draw_state->draw_rr_node,
985986
(device_ctx.rr_nodes.size()) * sizeof(t_draw_rr_node));
986-
for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
987-
draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
988-
draw_state->draw_rr_node[i].node_highlighted = false;
987+
/*FIXME: the type cast should be eliminated by making draw_rr_node adapt RRNodeId */
988+
for (const RRNodeId& rr_id : rr_graph.nodes()) {
989+
draw_state->draw_rr_node[(size_t)rr_id].color = DEFAULT_RR_NODE_COLOR;
990+
draw_state->draw_rr_node[(size_t)rr_id].node_highlighted = false;
989991
}
990992
}
991993
draw_coords->tile_width = width_val;
@@ -1310,28 +1312,28 @@ static void draw_routing_costs(ezgl::renderer* g) {
13101312
float max_cost = -min_cost;
13111313
std::vector<float> rr_node_costs(device_ctx.rr_nodes.size(), 0.);
13121314

1313-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
1315+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
13141316
float cost = 0.;
13151317
if (draw_state->show_routing_costs == DRAW_TOTAL_ROUTING_COSTS
13161318
|| draw_state->show_routing_costs
13171319
== DRAW_LOG_TOTAL_ROUTING_COSTS) {
1318-
cost = get_single_rr_cong_cost(inode,
1320+
cost = get_single_rr_cong_cost((size_t)rr_id,
13191321
get_draw_state_vars()->pres_fac);
13201322

13211323
} else if (draw_state->show_routing_costs == DRAW_BASE_ROUTING_COSTS) {
1322-
cost = get_single_rr_cong_base_cost(inode);
1324+
cost = get_single_rr_cong_base_cost((size_t)rr_id);
13231325

13241326
} else if (draw_state->show_routing_costs == DRAW_ACC_ROUTING_COSTS
13251327
|| draw_state->show_routing_costs
13261328
== DRAW_LOG_ACC_ROUTING_COSTS) {
1327-
cost = get_single_rr_cong_acc_cost(inode);
1329+
cost = get_single_rr_cong_acc_cost((size_t)rr_id);
13281330

13291331
} else {
13301332
VTR_ASSERT(
13311333
draw_state->show_routing_costs == DRAW_PRES_ROUTING_COSTS
13321334
|| draw_state->show_routing_costs
13331335
== DRAW_LOG_PRES_ROUTING_COSTS);
1334-
cost = get_single_rr_cong_pres_cost(inode,
1336+
cost = get_single_rr_cong_pres_cost((size_t)rr_id,
13351337
get_draw_state_vars()->pres_fac);
13361338
}
13371339

@@ -1341,15 +1343,15 @@ static void draw_routing_costs(ezgl::renderer* g) {
13411343
== DRAW_LOG_PRES_ROUTING_COSTS) {
13421344
cost = std::log(cost);
13431345
}
1344-
rr_node_costs[inode] = cost;
1346+
rr_node_costs[(size_t)rr_id] = cost;
13451347
min_cost = std::min(min_cost, cost);
13461348
max_cost = std::max(max_cost, cost);
13471349
}
13481350

13491351
//Hide min value, draw_rr_costs() ignores NaN's
1350-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
1351-
if (rr_node_costs[inode] == min_cost) {
1352-
rr_node_costs[inode] = NAN;
1352+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
1353+
if (rr_node_costs[(size_t)rr_id] == min_cost) {
1354+
rr_node_costs[(size_t)rr_id] = NAN;
13531355
}
13541356
}
13551357
char msg[vtr::bufsize];
@@ -1458,11 +1460,11 @@ void draw_rr(ezgl::renderer* g) {
14581460

14591461
g->set_line_dash(ezgl::line_dash::none);
14601462

1461-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
1462-
RRNodeId rr_node = RRNodeId(inode);
1463+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
1464+
size_t inode = (size_t)rr_id;
14631465
if (!draw_state->draw_rr_node[inode].node_highlighted) {
14641466
/* If not highlighted node, assign color based on type. */
1465-
switch (rr_graph.node_type(rr_node)) {
1467+
switch (rr_graph.node_type(rr_id)) {
14661468
case CHANX:
14671469
case CHANY:
14681470
draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
@@ -1485,7 +1487,7 @@ void draw_rr(ezgl::renderer* g) {
14851487
}
14861488

14871489
/* Now call drawing routines to draw the node. */
1488-
switch (rr_graph.node_type(rr_node)) {
1490+
switch (rr_graph.node_type(rr_id)) {
14891491
case SINK:
14901492
draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g);
14911493
break;
@@ -1516,7 +1518,7 @@ void draw_rr(ezgl::renderer* g) {
15161518

15171519
default:
15181520
vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
1519-
"in draw_rr: Unexpected rr_node type: %d.\n", rr_graph.node_type(rr_node));
1521+
"in draw_rr: Unexpected rr_node type: %d.\n", rr_graph.node_type(rr_id));
15201522
}
15211523
}
15221524

@@ -2718,22 +2720,22 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
27182720
}
27192721

27202722
/* Highlight the nodes that can fanin to this node in blue. */
2721-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
2722-
for (t_edge_size iedge = 0, l = rr_graph.num_edges(RRNodeId(inode)); iedge < l;
2723+
for (const RRNodeId& inode : rr_graph.nodes()) {
2724+
for (t_edge_size iedge = 0, l = rr_graph.num_edges(inode); iedge < l;
27232725
iedge++) {
2724-
int fanout_node = size_t(rr_graph.edge_sink_node(RRNodeId(node), iedge));
2726+
int fanout_node = size_t(rr_graph.edge_sink_node(inode, iedge));
27252727
if (fanout_node == node) {
27262728
if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA
2727-
&& draw_state->draw_rr_node[inode].color
2729+
&& draw_state->draw_rr_node[size_t(inode)].color
27282730
!= ezgl::MAGENTA) {
27292731
// If node is highlighted, highlight its fanin
2730-
draw_state->draw_rr_node[inode].color = ezgl::BLUE;
2731-
draw_state->draw_rr_node[inode].node_highlighted = true;
2732+
draw_state->draw_rr_node[size_t(inode)].color = ezgl::BLUE;
2733+
draw_state->draw_rr_node[size_t(inode)].node_highlighted = true;
27322734
} else if (draw_state->draw_rr_node[node].color
27332735
== ezgl::WHITE) {
27342736
// If node is de-highlighted, de-highlight its fanin
2735-
draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
2736-
draw_state->draw_rr_node[inode].node_highlighted = false;
2737+
draw_state->draw_rr_node[size_t(inode)].color = DEFAULT_RR_NODE_COLOR;
2738+
draw_state->draw_rr_node[size_t(inode)].node_highlighted = false;
27372739
}
27382740
}
27392741
}
@@ -2755,17 +2757,17 @@ static int draw_check_rr_node_hit(float click_x, float click_y) {
27552757
auto& device_ctx = g_vpr_ctx.device();
27562758
const auto& rr_graph = device_ctx.rr_graph;
27572759

2758-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
2759-
RRNodeId rr_node = RRNodeId(inode);
2760-
switch (rr_graph.node_type(rr_node)) {
2760+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
2761+
size_t inode = (size_t)rr_id;
2762+
switch (rr_graph.node_type(rr_id)) {
27612763
case IPIN:
27622764
case OPIN: {
2763-
int i = rr_graph.node_xlow(rr_node);
2764-
int j = rr_graph.node_ylow(rr_node);
2765+
int i = rr_graph.node_xlow(rr_id);
2766+
int j = rr_graph.node_ylow(rr_id);
27652767
t_physical_tile_type_ptr type = device_ctx.grid[i][j].type;
27662768
int width_offset = device_ctx.grid[i][j].width_offset;
27672769
int height_offset = device_ctx.grid[i][j].height_offset;
2768-
int ipin = rr_graph.node_pin_num(rr_node);
2770+
int ipin = rr_graph.node_pin_num(rr_id);
27692771
float xcen, ycen;
27702772
for (const e_side& iside : SIDES) {
27712773
// If pin exists on this side of the block, then get pin coordinates
@@ -3053,7 +3055,8 @@ void deselect_all() {
30533055
for (auto net_id : cluster_ctx.clb_nlist.nets())
30543056
draw_state->net_color[net_id] = ezgl::BLACK;
30553057

3056-
for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
3058+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
3059+
size_t i = (size_t)rr_id;
30573060
draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
30583061
draw_state->draw_rr_node[i].node_highlighted = false;
30593062
}
@@ -4140,17 +4143,17 @@ static void draw_router_expansion_costs(ezgl::renderer* g) {
41404143

41414144
std::vector<float> rr_costs(device_ctx.rr_nodes.size());
41424145

4143-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
4146+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
41444147
float cost = get_router_expansion_cost(
4145-
routing_ctx.rr_node_route_inf[inode],
4148+
routing_ctx.rr_node_route_inf[(size_t)rr_id],
41464149
draw_state->show_router_expansion_cost);
4147-
rr_costs[inode] = cost;
4150+
rr_costs[(size_t)rr_id] = cost;
41484151
}
41494152

41504153
bool all_nan = true;
4151-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
4152-
if (std::isinf(rr_costs[inode])) {
4153-
rr_costs[inode] = NAN;
4154+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
4155+
if (std::isinf(rr_costs[(size_t)rr_id])) {
4156+
rr_costs[(size_t)rr_id] = NAN;
41544157
} else {
41554158
all_nan = false;
41564159
}
@@ -4199,11 +4202,11 @@ static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs,
41994202

42004203
float min_cost = std::numeric_limits<float>::infinity();
42014204
float max_cost = -min_cost;
4202-
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
4203-
if (std::isnan(rr_costs[inode])) continue;
4205+
for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) {
4206+
if (std::isnan(rr_costs[(size_t)rr_id])) continue;
42044207

4205-
min_cost = std::min(min_cost, rr_costs[inode]);
4206-
max_cost = std::max(max_cost, rr_costs[inode]);
4208+
min_cost = std::min(min_cost, rr_costs[(size_t)rr_id]);
4209+
max_cost = std::max(max_cost, rr_costs[(size_t)rr_id]);
42074210
}
42084211
if (min_cost == std::numeric_limits<float>::infinity()) min_cost = 0;
42094212
if (max_cost == -std::numeric_limits<float>::infinity()) max_cost = 0;

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